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OMAP3530 Datasheet(PDF) 13 Page - Texas Instruments |
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OMAP3530 Datasheet(HTML) 13 Page - Texas Instruments |
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13 / 230 page  www.ti.com OMAP3530/25 Applications Processor SPRS507 – FEBRUARY 2008 Table 2-1. Ball Characteristics (CBB Pkg.)(1) (continued) BALL BALL PIN MODE TYPE BALL BALL RESET POWER [9] HYS BUFFER PULL IO BOTTOM TOP NAME [3] [4] [5] RESET RESET REL. [10] STRENGTH U/D CELL [13] [1] [2] STATE REL. MODE (mA) [11] TYPE [6] STATE [8] [12] [7] B13 B9 sdrc_d22 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ LVCMOS PD D14 A9 sdrc_d23 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ LVCMOS PD C18 B21 sdrc_d24 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ LVCMOS PD A19 A21 sdrc_d25 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ LVCMOS PD B19 D22 sdrc_d26 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ LVCMOS PD B20 D23 sdrc_d27 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ LVCMOS PD D20 E22 sdrc_d28 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ LVCMOS PD A21 E23 sdrc_d29 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ LVCMOS PD B21 G22 sdrc_d30 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ LVCMOS PD C21 G23 sdrc_d31 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ LVCMOS PD H9 AB21 sdrc_ba0 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS H10 AC21 sdrc_ba1 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS A4 N22 sdrc_a0 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS B4 N23 sdrc_a1 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS B3 P22 sdrc_a2 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS C5 P23 sdrc_a3 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS C4 R22 sdrc_a4 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS D5 R23 sdrc_a5 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS C3 T22 sdrc_a6 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS C2 T23 sdrc_a7 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS C1 U22 sdrc_a8 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS D4 U23 sdrc_a9 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS D3 V22 sdrc_a10 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS D2 V23 sdrc_a11 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS D1 W22 sdrc_a12 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS E2 W23 sdrc_a13 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS E1 Y22 sdrc_a14 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS H11 M22 sdrc_ncs0 0 O 1 1 0 VDDS_ MEM No 4 NA LVCMOS H12 M23 sdrc_ncs1 0 O 1 1 0 VDDS_ MEM No 4 NA LVCMOS A13 A11 sdrc_clk 0 IO L 0 0 VDDS_ MEM Yes 4 PU/ LVCMOS PD A14 B11 sdrc_nclk 0 O 1 1 0 VDDS_ MEM No 4 NA LVCMOS H16 J22 sdrc_cke0 0 O H 1 7 VDDS_ MEM Yes 4 PU/ LVCMOS PD safe_mode 7 H17 J23 sdrc_cke1 0 O H 1 7 VDDS_ MEM Yes 4 PU/ LVCMOS PD safe_mode 7 H14 L23 sdrc_nras 0 O 1 1 0 VDDS_ MEM No 4 NA LVCMOS H13 L22 sdrc_ncas 0 O 1 1 0 VDDS_ MEM No 4 NA LVCMOS Submit Documentation Feedback TERMINAL DESCRIPTION 13 |
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