OMAP3530 datasheet(2/230 Pages) TI

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OMAP3530/25 Applications Processor

SPRS507 – FEBRUARY 2008

–

Rotation 90-, 180-, and 270-degrees

• External Memory Interfaces:

–

Resize Images From 1/4x to 8x

–

SDRAM Controller (SDRC)

–

Color Space Converter

• 16, 32-bit Memory Controller With

2G-Byte Total Address Space

–

8-bit Alpha Blending

• Interfaces to Low-Power Double Data

• Serial Communication

Rate (LPDDR) SDRAM

–

5 Multichannel Buffered Serial Ports

• SDRAM Memory Scheduler (SMS) and

(McBSPs)

Rotation Engine

• 512 Byte Transmit/Receive Buffer

–

General Purpose Memory Controller

(McBSP1/3/4/5)

(GPMC)

• 5K-Byte Transmit/Receive Buffer

• 16-bit Wide Multiplexed Address/Data

(McBSP2)

Bus

• SIDETONE Core Support (McBSP2 and 3

• Up to 8 Chip Select Pins With 129M-Byte

Only) For Filter, Gain, and Mix

Address Space per Chip Select Pin

Operations

• Glueless Interface to NOR Flash, NAND

• Direct Interface to I2S and PCM Device

Flash (With ECC Hamming Code

and TDM Buses

Calculation), SRAM and Pseudo-SRAM

• 128 Channel Transmit/Receive Mode

• Flexible Asynchronous Protocol Control

–

Four Master/Slave Multichannel Serial Port

for Interface to Custom Logic (FPGA,

Interface (McSPI) Ports

CPLD, ASICs, etc.)

–

High-Speed/Full-Speed/Low-Speed USB

• Nonmultiplexed Address/Data Mode

OTG Controller (12-/8-Pin ULPI Interface)

(Limited 2K-Byte Address Space)

–

High-Speed/Full-Speed/Low-Speed

• System Direct Memory Access (sDMA)

Multiport USB Host Controller

Controller (32 Logical Channels With

• 12-/8-Pin ULPI Interface or 6-/4-/3-Pin

Configurable Priority)

Serial Interface

• Camera Image Signal Processing (ISP)

• Supports Transceiverless Link Logic

(TLL)

–

CCD and CMOS Imager Interface

–

One HDQ/1-Wire Interface

–

Memory Data Input

–

Three UARTs (One with Infrared Data

–

RAW Data Interface

Association [IrDA] and Consumer Infrared

–

BT.601/BT.656 Digital YCbCr 4:2:2

[CIR] Modes)

(8-/16-Bit) Interface

–

Three Master/Slave High-Speed

–

A-Law Compression and Decompression

Inter-Integrated Circuit (I2C) Controllers

–

Preview Engine for Real-Time Image

• Removable Media Interfaces:

Processing

–

Three Multimedia Card (MMC)/ Secure

–

Glueless Interface to Common Video

Digital (SD) With Secure Data I/O (SDIO)

Decoders

–

Histogram Module/Auto-Exposure,

• Comprehensive Power, Reset, and Clock

Auto-White Balance, and Auto-Focus

Management

Engine

–

SmartReflex™ Technology

–

Resize Engine

–

Dynamic Voltage and Frequency Scaling

• Resize Images From 1/4x to 4x

(DVFS)

• Separate Horizontal/Vertical Control

• Test Interfaces

• Display Subsystem

–

IEEE-1149.1 (JTAG) Boundary-Scan

Compatible

–

Parallel Digital Output

–

Embedded Trace Macro Interface (ETM)

• Up to 24-Bit RGB

–

Serial Data Transport Interface (SDTI)

• HD Maximum Resolution

• Supports Up to 2 LCD Panels

• 12 32-bit General Purpose Timers

• Support for Remote Frame Buffer

• 2 32-bit Watchdog Timers

Interface (RFBI) LCD Panels

• 1 32-bit 32-kHz Sync Timer

–

2 10-Bit Digital-to-Analog Converters

• Up to 188 General-Purpose I/O (GPIO) Pins

(DACs) Supporting:

(Multiplexed With Other Device Functions)

• Composite NTSC/PAL Video

• 65-nm CMOS Technology

• Luma/Chroma Separate Video (S-Video)

OMAP3530/25 Applications Processor

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