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LAN9312 Datasheet(PDF) 37 Page - SMSC Corporation

Part # LAN9312
Description  High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
PDF  458 Pages
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Manufacturer  SMSC [SMSC Corporation]
Direct Link  http://www.smsc.com
Logo SMSC - SMSC Corporation

LAN9312 Datasheet(HTML) 37 Page - SMSC Corporation

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High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
37
Revision 1.2 (04-08-08)
DATASHEET
Note 4.1
In the case of a soft reset, the EEPROM Loader is run, but loads only the MAC address
into the Host MAC. No other values are loaded by the EEPROM Loader in this case.
4.2.1
Chip-Level Resets
A chip-level reset event activates all internal resets, effectively resetting the entire LAN9312.
Configuration straps are latched, and the EEPROM Loader is run as a result of chip-level resets. A
chip-level reset is initiated by assertion of any of the following input events:
Power-On Reset (POR)
nRST Pin Reset
Chip-level reset completion/configuration can be determined by polling the READY bit of the Hardware
Configuration Register (HW_CFG) or Power Management Control Register (PMT_CTRL) until it is set.
When set, the READY bit indicates that the reset has completed and the device is ready to be
accessed.
With the exception of the Hardware Configuration Register (HW_CFG), Power Management Control
Register (PMT_CTRL), Byte Order Test Register (BYTE_TEST), and Reset Control Register
(RESET_CTL), read access to any internal resources is forbidden while the READY bit is cleared.
Writes to any address are invalid until the READY bit is set.
Note: The LAN9312 must be read at least once after any chip-level reset to ensure that write
operations function properly.
4.2.1.1
Power-On Reset (POR)
A power-on reset occurs whenever power is initially applied to the LAN9312, or if the power is removed
and reapplied to the LAN9312. This event resets all circuitry within the device. Configuration straps
are latched, and the EEPROM Loader is run as a result of this reset.
Table 4.1 Reset Sources and Affected LAN9312 Circuitry
RESET SOURCE
POR
XXXX
XXXXX
X
X
nRST Pin
XXXX
XXXXX
X
X
Digital Reset
XXX
XXXXX
X
Soft Reset
XX
Note 4.1
Port 2 PHY
X
Port 1 PHY
X
Virtual PHY
X



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