LAN9312 datasheet(96/458 Pages) SMSC

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High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

Revision 1.2 (04-08-08)

SMSC LAN9312

DATASHEET

7.2.10.2

PHY Software Reset via PHY_BASIC_CTRL_x

The PHY can also be reset by setting bit 15 (PHY_RST) of the Port x PHY Basic Control Register

(PHY_BASIC_CONTROL_x). This bit is self clearing and will return to 0 after the reset is complete.

This reset does not reload the configuration strap values into the PHY registers.

7.2.10.3

PHY Power-Down Reset

After the PHY has returned from a power-down state, a reset of the PHY is automatically generated.

The PHY power-down modes do not reload or reset the PHY registers. Refer to Section 7.2.9, "PHY

Power-Down Modes," on page 94 for additional information.

7.2.11

LEDs

Each PHY provides LED indication signals to the GPIO/LED block of the LAN9312. This allows

external LEDs to be used to indicate various PHY related functions such as TX/RX activity, speed,

duplex, or link status. Refer to Chapter 13, "GPIO/LED Controller," on page 162 for additional

information on the configuration of these signals.

7.2.12

Required Ethernet Magnetics

The magnetics selected for use with the LAN9312 should be an Auto-MDIX style magnetic, which is

widely available from several vendors. Please review the SMSC Application note 8.13 “Suggested

Magnetics” for the latest qualified and suggested magnetics. A list of vendors and part numbers are

provided within the application note.

7.3

Virtual PHY

The Virtual PHY provides a basic MII management interface (MDIO) to the Host MAC per the IEEE

802.3 (clause 22) so that an unmodified driver can be supported as if the Host MAC was attached to

a single port PHY. This functionality is designed to allow easy and quick integration of the LAN9312

into designs with minimal driver modifications. The Virtual PHY provides a full bank of registers which

comply with the IEEE 802.3 specification. This enables the Virtual PHY to provide various status and

control bits similar to those provided by a real PHY. These include the output of speed selection,

duplex, loopback, isolate, collision test, and auto-negotiation status. For a list of all Virtual PHY

registers and related bit descriptions, refer to Section 14.4.1, "Virtual PHY Registers," on page 286.

7.3.1

Virtual PHY Auto-Negotiation

The purpose of the auto-negotiation function is to automatically configure the Virtual PHY to the

optimum link parameters based on the capabilities of its link partner. Because the Virtual PHY has no

actual link partner, the auto-negotiation process is emulated with deterministic results.

Auto-negotiation is enabled by setting bit 12 (VPHY_AN) of the Virtual PHY Basic Control Register

(VPHY_BASIC_CTRL) and is restarted by the occurrence of any of the following events:

Power-On Reset (POR)

Hardware reset (nRST)

PHY Software reset (via bit 3 of the Reset Control Register (RESET_CTL), bit 0 of the Power

Management Control Register (PMT_CTRL), or bit 15 of the Virtual PHY Basic Control Register

(VPHY_BASIC_CTRL))

Setting the Virtual PHY Basic Control Register (VPHY_BASIC_CTRL), bit 9 high (auto-neg restart)

Digital Reset (via bit 10 of the Reset Control Register (RESET_CTL))

Issuing an EEPROM Loader RELOAD command (Section 10.2.4, "EEPROM Loader," on page 149)

The emulated auto-negotiation process is much simpler than the real process and can be categorized

into three steps:

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