M68AF127B datasheet(7/23 Pages) STMICROELECTRONICS

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M68AF127B

OPERATION

The M68AF127B has a Chip Enable power down

feature which invokes an automatic standby mode

whenever Chip Enable is de-asserted (E1 = High),

or Chip Select is asserted (E2 = Low). An Output

Enable (G) signal provides a high-speed, tri-state

control, allowing fast read/write cycles to be

achieved with the common I/O data bus. Opera-

tional modes are determined by device control in-

puts W and E1 as summarized in the Operating

Modes table (Table 2).

Read Mode

The M68AF127B is in the Read mode whenever

Write Enable (W) is High with Output Enable (G)

Low, Chip Enable (E1) is asserted and Chip Select

(E2) is de-asserted. This provides access to data

from eight of the 1,048,576 locations in the static

memory array, specified by the 17 address inputs.

Valid data will be available at the eight output pins

within tAVQV after the last stable address, provid-

ing G is Low and E1 is Low. If Chip Enable or Out-

put Enable access times are not met, data access

will be measured from the limiting parameter

(tELQV or tGLQV) rather than the address. Data out

may be indeterminate at tELQX and tGLQX, but data

lines will always be valid at tAVQV.

Write Mode

The M68AF127B is in the Write mode whenever

the W and E1 pins are Low and the E2 pin is High.

Either the Chip Enable input (E1) or the Write En-

able input (W) must be de-asserted during Ad-

dress transitions for subsequent write cycles.

Write begins with the concurrence of E1 being ac-

tive with W low. Therefore, address setup time is

referenced to Write Enable and Chip Enable as

tAVWL and tAVEH, respectively, and is determined

by the latter occurring edge.

The Write cycle can be terminated by the earlier

rising edge of E1, or W.

If the Output is enabled (E1 = Low, E2 = High and

G = Low), then W will return the outputs to high im-

pedance within tWLQZ of its falling edge. Care must

be taken to avoid bus contention in this type of op-

eration. Data input must be valid for tDVWH before

the rising edge of Write Enable, or for tDVEH before

the rising edge of E1, whichever occurs first, and

remain valid for tWHDX or tEHDX.

Table 2. Operating Modes

Note: X = VIH or VIL.

Operation

DQ0-DQ7

Power

Read

VIL

VIH

Hi-Z

Active (ICC)

Read

VIL

VIH

VIL

Data Output

Active (ICC)

Write

VIL

VIH

VIL

Data Input

Active (ICC)

Deselect

VIH

Hi-Z

Standby (ISB)

Deselect

VIL

Hi-Z

Standby (ISB)

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