M7010R datasheet(33/67 Pages) STMICROELECTRONICS

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M7010R

Table 22. (Single) WRITE Address Format for Data and Mask Arrays or SRAM

Note: 1. “|” stands for logical OR operation, and “{}” stands for concatenation operator.

Table 23. WRITE Address Format for Internal Registers

Table 24. WRITE Address Format for Data and Mask Array (Burst WRITE)

[67:30]

[29]

[28:26]

[25:21]

[20:19]

[18:14]

[13:0]

Reserved

0: Direct

1: Indirect

Successful

(Applicable if

DQ[29] is

indirect)

00: Data

Array

Reserved

If DQ[29] is '0,' this field carries the

address of the data array location.

If DQ[29] is '1,' the SSR specified on

DQ[28:26] is used to generate the

address of the data array location:

{SSR[13:2], SSR[1] | DQ[1], SSR[0]

| DQ[0]}.(1)

Reserved

0: Direct

1: Indirect

Successful

(Applicable if

DQ[29] is

indirect)

01: Mask

Array

Reserved

If DQ[29] is '0,' this field carries

address of the mask array location.

If DQ[29] is '1,' the SSR specified on

DQ[28:26] is used to generate the

address of the data array location:

{SSR[13:2], SSR[1] | DQ[1], SSR[0]

| DQ[0]}.(1)

Reserved

0: Direct

1: Indirect

Successful

(Applicable if

DQ[29] is

indirect)

10: External

SRAM

Reserved

If DQ[29] is '0,' this field carries

address of the data SRAM location.

If DQ[29] is '1,' the SSR specified on

DQ[28:26] is used to generate the

address of the data array location:

{SSR[13:2], SSR[1] | DQ[1], SSR[0]

| DQ[0]}.(1)

DQ[67:26]

DQ[25:21]

DQ[20:19]

DQ[18:6]

DQ[5:0]

Reserved

11: Register

Reserved

[67:26]

[25:21]

[20:19]

[18:14]

[13:0]

Reserved

00: Data array

Reserved

Don’t care. These 14 bits come from the

internal register (WBURADR), which

increments with each access.

Reserved

01: Mask array

Reserved

Don’t care. These 14 bits come from the

internal register (WBURADR), which

increments with each access.

M7010R Datasheet(PDF) 33 Page - STMicroelectronics

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