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M7010R Datasheet(PDF) 49 Page - STMicroelectronics |
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M7010R Datasheet(HTML) 49 Page - STMicroelectronics |
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49 / 67 page  49/67 M7010R LEARN is a pipelined operation and last for two CLK cycles where TLSZ = 00, as shown in Figure 35, page 49, and TLSZ = 01, as shown in Figure 36, page 50 and Figure 37, page 51. Figure 36 and Figure 37 assume that the device performing the LEARN operation is not the last device in the table and has its LRAM Bit set to '0.' Note: The OE_L for the device with the LRAM Bit set goes high for two cycles for each LEARN (one during the SRAM WRITE cycle, and one during the cycle before it). The latency of the SRAM WRITE cycle from the second cycle of the instruc- tion is shown in Table 34, page 51. Figure 35. LEARN Command Timing Diagram (TLSZ = 00) Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 7 Cycle 6 Cycle 8 Cycle 10 Cycle 9 CLK2X CMDV CMD[1:0] ALE_L, CE_L WE_L OE_L SADR[21:0] SSV SSF CMD[8:2] PHS_L AI04289 A BX X XX XX DQ A1 1 1 11 1 1 0 0 0 0 0 1 0 0 0 A2 Learn1 Learn2 X X TLSZ = 00, LRAM = 1, LDEV = 1 Comp1 Comp2 1A 1B |
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