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RA4E1 Datasheet(PDF) 29 Page - Renesas Technology Corp |
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RA4E1 Datasheet(HTML) 29 Page - Renesas Technology Corp |
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29 / 81 page  Table 2.16 Operation frequency value in Subosc-speed mode Parameter Symbol Min Typ Max Unit Operation frequency System clock (ICLK) f 29.4 — 36.1 kHz Peripheral module clock (PCLKA) — — 36.1 Peripheral module clock (PCLKB) — — 36.1 Peripheral module clock (PCLKC) *2 — — 36.1 Peripheral module clock (PCLKD) — — 36.1 Flash interface clock (FCLK)*1 29.4 — 36.1 Note 1. Programming or erasing the flash memory is disabled in Subosc-speed mode. Note 2. The ADC12 cannot be used. 2.3.2 Clock Timing Table 2.17 Clock timing except for sub-clock oscillator (1 of 2) Parameter Symbol Min Typ Max Unit Test conditions EXTAL external clock input cycle time tEXcyc 41.66 — — ns Figure 2.7 EXTAL external clock input high pulse width tEXH 15.83 — — ns EXTAL external clock input low pulse width tEXL 15.83 — — ns EXTAL external clock rise time tEXr — — 5.0 ns EXTAL external clock fall time tEXf — — 5.0 ns Main clock oscillator frequency fMAIN 8 — 24 MHz — Main clock oscillation stabilization wait time (crystal)*1 tMAINOSCWT — — —*1 ms Figure 2.8 LOCO clock oscillation frequency fLOCO 29.4912 32.768 36.0448 kHz — LOCO clock oscillation stabilization wait time tLOCOWT — — 60.4 µs Figure 2.9 ILOCO clock oscillation frequency fILOCO 13.5 15 16.5 kHz — MOCO clock oscillation frequency fMOCO 6.8 8 9.2 MHz — MOCO clock oscillation stabilization wait time tMOCOWT — — 15.0 µs — HOCO clock oscillator oscillation frequency Without FLL fHOCO16 15.78 16 16.22 MHz –20 ≤ Ta ≤ 85°C fHOCO18 17.75 18 18.25 fHOCO20 19.72 20 20.28 fHOCO16 15.71 16 16.29 –40 ≤ Ta ≤ –20°C fHOCO18 17.68 18 18.32 fHOCO20 19.64 20 20.36 With FLL fHOCO16 15.960 16 16.040 –40 ≤ Ta ≤ 85°C Sub-clock frequency accuracy is ±50 ppm. fHOCO18 17.955 18 18.045 fHOCO20 19.950 20 20.050 HOCO clock oscillation stabilization wait time*2 tHOCOWT — — 64.7 µs — HOCO period jitter — — ±85 — ps — FLL stabilization wait time tFLLWT — — 1.8 ms — PLL clock frequency fPLL 100 — 200 MHz — PLL2 clock frequency fPLL2 120 — 240 MHz — PLL/PLL2 clock oscillation stabilization wait time tPLLWT — — 174.9 µs Figure 2.10 RA4E1 Datasheet 2. Electrical Characteristics R01DS0391EJ0130 Rev.1.30 Jun 6, 2025 Page 29 of 81 |
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