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2.3.11

IIC Timing

Table 2.29

IIC timing (1) (1 of 2)

(1) Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register for the following pins: SDA0_B,

SCL0_B.

(2) The following pins do not require setting: SCL0_A, SDA0_A.

(3) Use pins that have a letter appended to their names, for instance “_A” or “_B”, to indicate group membership. For the IIC interface, the

AC portion of the electrical characteristics is measured for each group.

Parameter

Symbol

Min

Max

Unit

Test

conditions

IIC

(Standard mode,

SMBus)

ICFER.FMPE = 0

SCL input cycle time

tSCL

6 (12) × tIICcyc + 1300

—

Figure 2.42

SCL input high pulse width

tSCLH

3 (6) × tIICcyc + 300

—

SCL input low pulse width

tSCLL

3 (6) × tIICcyc + 300

—

SCL, SDA rise time

tSr

—

1000

SCL, SDA fall time

tSf

—

300

SCL, SDA input spike pulse

removal time

tSP

1 (4) × tIICcyc ns

SDA input bus free time when

wakeup function is disabled

tBUF

3 (6) × tIICcyc + 300

—

SDA input bus free time when

wakeup function is enabled

tBUF

3 (6) × tIICcyc + 4 × tPcyc +

300

—

START condition input hold time

when wakeup function is disabled

tSTAH

tIICcyc + 300

—

START condition input hold time

when wakeup function is enabled

tSTAH

1 (5) × tIICcyc + tPcyc + 300

—

Repeated START condition input

setup time

tSTAS

1000

—

STOP condition input setup time

tSTOS

1000

—

Data input setup time

tSDAS

tIICcyc + 50

—

Data input hold time

tSDAH

—

SCL, SDA capacitive load

Cb*2

—

400

RA4E1 Datasheet

2. Electrical Characteristics

R01DS0391EJ0130 Rev.1.30

Jun 6, 2025

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