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R5F5651CDDFB Datasheet(PDF) 136 Page - Renesas Technology Corp |
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R5F5651CDDFB Datasheet(HTML) 136 Page - Renesas Technology Corp |
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136 / 188 page ![]() R01DS0276EJ0240 Rev.2.40 Page 136 of 188 Oct 31, 2023 RX65N Group, RX651 Group 2. Electrical Characteristics Note 1. tPcyc refers to the period of PCLKA in SCI10 and SCI11, and of PCLKB in SCI0 to SCI9, and SCI12. Figure 2.49 Simple SPI Clock Timing Table 2.37 Simple SPI Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr, Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF, High-drive output is selected by the driving ability control register. Item Symbol Min. Max. Unit*1 Test Conditions Simple SPI SCK clock cycle output (master) tSPcyc 4 65536 tPcyc Figure 2.49 SCK clock cycle input (slave) 6 65536 SCK clock high pulse width tSPCKWH 0.4 0.6 tSPcyc SCK clock low pulse width tSPCKWL 0.4 0.6 tSPcyc SCK clock rise/fall time tSPCKr, tSPCKf —20 ns Data input setup time tSU 33.3 — ns Figure 2.50 to Figure 2.53 Data input hold time tH 33.3 — ns SS input setup time tLEAD 1— tSPcyc SS input hold time tLAG 1— tSPcyc Data output delay time tOD — 33.3 ns Data output hold time tOH –10 — ns Data rise/fall time tDr, tDf — 16.6 ns SS input rise/fall time tSSLr, tSSLf — 16.6 ns Slave access time tSA —5 tPcyc Figure 2.52, Figure 2.53 Slave output release time tREL —5 tPcyc tSPCKWH VOH VOH VOL VOL VOH VOH tSPCKWL tSPCKr tSPCKf VOL tSPcyc tSPCKWH VIH VIH VIL VIL VIH VIH tSPCKWL tSPCKr tSPCKf VIL tSPcyc VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC (n = 0 to 12) SCKn master select output SCKn slave select input |
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