R5F56517FDFM datasheet(29/188 Pages) RENESAS

29 / 188 page

RX65N Group, RX651 Group

1. Overview

R01DS0276EJ0240 Rev.2.40

Page 29 of 188

Oct 31, 2023

Multiplexed bus

A0/D0 to A15/D15

I/O

Address/data multiplexed bus

Bus control

RD#

Output

Strobe signal which indicates that reading from the external bus

interface space is in progress

WR#

Output

Strobe signal which indicates that writing to the external bus

interface space is in progress, in 1-write strobe mode

WR0# to WR3#

Output

Strobe signals which indicate that either group of data bus pins

(D7 to D0, D15 to D8, D23 to D16 and D31 to D24) is valid in

writing to the external bus interface space, in byte strobe mode

BC0# to BC3#

Output

Strobe signals which indicate that either group of data bus pins

(D7 to D0, D15 to D8, D23 to D16 and D31 to D24) is valid in

access to the external bus interface space, in 1-write strobe

mode

ALE

Output

Address latch signal when address/data multiplexed bus is

selected

WAIT#

Input

Input pin for wait request signals in access to the external space

CS0# to CS7#

Output

Select signals for CS areas

CKE

Output

SDRAM clock enable signal

SDCS#

Output

SDRAM chip select signal

RAS#

Output

SDRAM row address strobe signal

CAS#

Output

SDRAM column address strove signal

WE#

Output

SDRAM write enable pin

DQM0 to DQM3

Output

SDRAM I/O data mask enable signals

EXDMA controller

EDREQ0, EDREQ1

Input

External DMA transfer request pins

EDACK0, EDACK1

Output

Single address transfer acknowledge signals

Interrupt

NMI

Input

Non-maskable interrupt request pin

IRQ0 to IRQ15, IRQ0-DS to

IRQ15-DS

Input

Maskable interrupt request pins

Multi-function timer pulse

unit 3

MTIOC0A, MTIOC0B,

MTIOC0C, MTIOC0D

I/O

The TGRA0 to TGRD0 input capture input/output compare

output/PWM output pins

MTIOC1A, MTIOC1B

I/O

The TGRA1 and TGRB1 input capture input/output compare

output/PWM output pins

MTIOC2A, MTIOC2B

I/O

The TGRA2 and TGRB2 input capture input/output compare

output/PWM output pins

MTIOC3A, MTIOC3B,

MTIOC3C, MTIOC3D

I/O

The TGRA3 to TGRD3 input capture input/output compare

output/PWM output pins

MTIOC4A, MTIOC4B,

MTIOC4C, MTIOC4D

I/O

The TGRA4 to TGRD4 input capture input/output compare

output/PWM output pins

MTIC5U, MTIC5V, MTIC5W

Input

The TGRU5, TGRV5, and TGRW5 input capture input/dead

time compensation input pins

MTIOC6A, MTIOC6B,

MTIOC6C, MTIOC6D

I/O

The TGRA6 to TGRD6 input capture input/output compare

output/PWM output pins

MTIOC7A, MTIOC7B,

MTIOC7C, MTIOC7D

I/O

The TGRA7 to TGRD7 input capture input/output compare

output/PWM output pins

MTIOC8A, MTIOC8B,

MTIOC8C, MTIOC8D

I/O

The TGRA8 to TGRD8 input capture input/output compare

output/PWM output pins

MTCLKA, MTCLKB,

MTCLKC, MTCLKD

Input

Input pins for external clock signals or for phase counting mode

clock signals

Port output enable 3

POE0#, POE4#, POE8#,

POE10#, POE11#

Input

Input pins for request signals to place the MTU in the high

impedance state

Table 1.4

Pin Functions (2/8)

Classifications

Pin Name

I/O

Description

R5F56517FDFM Datasheet(PDF) 29 Page - Renesas Technology Corp

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