| Electronic Components Datasheet Search |
|
R5F5671CDDFM Datasheet(PDF) 8 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
R5F5671CDDFM Datasheet(HTML) 8 Page - Renesas Technology Corp |
|
8 / 179 page ![]() RX671 Group 1. Overview R01DS0373EJ0120 Rev.1.20 Page 8 of 179 Sep 30, 2024 Communication function Serial communications interfaces (RSCI) 2 channels (RSCI10, RSCI11) Serial communications modes: Asynchronous, clock synchronous, and smart-card interface Multi-processor function On-chip baud rate generator allows selection of the desired bit rate Choice of LSB-first or MSB-first transfer Start-bit detection: Level or edge detection is selectable. Simple I2C Simple SPI 9-bit transfer mode Bit rate modulation Double-speed mode Event linking by the ELC (only RSCI10) Supports the serial communications protocol, which contains the start frame and information frame Supports the LIN format Data can be transmitted or received in sequence by the 32-byte FIFO buffers of the transmission and reception unit Manchester encoding is supported. HBS (home bus system) support mode Data match detection Adjustment of the timing of sampling of the RXD signals I2C bus interface (RIICa) 3 channels (only channel 0 can be used in fast-mode plus) Communication formats I2C bus format/SMBus format Supports the multi-master Max. transfer rate: 1 Mbps (channel 0) Event linking by the ELC High-speed I2C bus interface (RIICHS) 1 channel Communication formats I2C bus format/SMBus format Supports the multi-master Max. transfer rate: 3.4 Mbps Event linking by the ELC CAN module (CAN) 2 channels Compliance with the ISO11898-1 specification (standard frame and extended frame) 32 mailboxes per channel Serial peripheral interface (RSPId) 3 channels RSPI transfer facility Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select), and RSPCK (RSPI clock) signals enables serial transfer through SPI operation (four lines) or clock-synchronous operation (three lines) Capable of handling serial transfer as a master or slave Data formats Switching between MSB first and LSB first The number of bits in each transfer can be changed to any number of bits from 8 to 16, or to 20, 24, or 32 bits. 128-bit buffers for transmission and reception Up to four frames can be transmitted or received in a single transfer operation (with each frame having up to 32 bits) Transmit/receive data can be swapped in byte units Buffered structure Double buffers for both transmission and reception RSPCK can be stopped with the receive buffer full for master reception. Event linking by the ELC Table 1.1 Outline of Specifications (7/10) Classification Module/Function Description |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |