R5F5671CDDFM datasheet(9/179 Pages) RENESAS

9 / 179 page

RX671 Group

1. Overview

R01DS0373EJ0120 Rev.1.20

Page 9 of 179

Sep 30, 2024

Communication

function

Serial peripheral

interface (RSPIA)

 1 channel

 RSPI transfer facility

Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select),

and RSPCK (RSPI clock) signals enables serial transfer through SPI operation (four

lines) or clock-synchronous operation (three lines)

Capable of handling serial transfer as a master or slave

 Data formats

Switching between MSB first and LSB first

The number of bits in each transfer can be changed to any number of bits from 8 to 16,

or to 20, 24, or 32 bits.

128-bit buffers for transmission and reception

Up to four frames can be transmitted or received in a single transfer operation (with

each frame having up to 32 bits)

Transit/receive data can be swapped in byte units

 Buffered structure

The transmission and reception sections have 4-stage and 32-bit-wide FIFO buffers for

the sequential transmission and reception of data.

 RSPCK can be stopped with the receive buffer full for master reception.

 Event linking by the ELC

 Communications protocol: RSPIA supports the Texas Instruments Synchronous Serial

Protocol (TI SSP).

Quad-SPI memory

interface (QSPIX)

 1 channel

 This interface can handle fetching from serial flash memory that has an SPI-compatible

interface.

 It supports extended SPI, dual-SPI, and quad-SPI protocols.

 Address width is selectable from among 8, 16, 24, and 32 bits.

Remote control signal

receiver (REMCa)

 1 channel

 Four pattern matching (header, data 0, data 1, and special data detection)

 8-byte receive buffer per unit

 The operating clock can be selected from among the PCLK, sub-clock, and TMR.

Serial sound interface (SSIE)

 1 channel

 Full-duplex transmission

 Various types of serial audio formatting are supported.

 Master and slave operations are supported.

 The bit-clock frequency is selectable from among 13 frequencies (1/1, 1/2, 1/4, 1/6, 1/8,

1/12, 1/16, 1/24, 1/32, 1/48, 1/64, 1/96, or 1/128).

 Data formats with 8, 16, 18, 20, 22, 24, and 32 bits are supported.

 32-stage FIFO buffers for transmission and reception

 Stopping or not stopping the SSILRCK signal on stopping of data transmission is

selectable.

SD host interface (SDHI)

 1 channel

 Transfer speed: Supports high-speed mode (25 MB/s) and default speed mode (12.5 MB/s)

 One interface for SD memory and I/O cards (supporting 1- and 4-bit SD buses)

 SD specifications

Part 1: Physical Layer Specification Ver. 3.01 compliant (DDR not supported)

Part E1: SDIO Specification Ver. 3.00

 Error checking: CRC7 for commands and CRC16 for data

 Interrupt requests: Card access interrupt, SDIO access interrupt, card detection

interrupt, SD buffer access interrupt

 DMA transfer requests: SD_BUF write and SD_BUF read

 Support for card detection and write protection

Table 1.1

Outline of Specifications (8/10)

Classification

Module/Function

Description

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