R5F5671CDDFM datasheet(102/179 Pages) RENESAS

102 / 179 page

R01DS0373EJ0120 Rev.1.20

Page 102 of 179

Sep 30, 2024

RX671 Group

2. Electrical Characteristics

2.4.5

Bus Timing

Table 2.26

Bus Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

ICLK = PCLKA = 8 to 120 MHz, PCLKB = BCLK = SDCLK = 8 to 60 MHz, Ta = Topr,

Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,

High-drive output is selected by the drive capacity control register.

Item

Symbol

Min.

Max.

Unit

Test Conditions

Address delay time

tAD

—

12.5

Figure 2.17 to

Figure 2.22

Byte control delay time

tBCD

—

12.5

CS# delay time

tCSD

—

12.5

ALE delay time

tALED

—

12.5

RD# delay time

tRSD

—

12.5

Read data setup time

tRDS

12.5

—

Read data hold time

tRDH

0—

WR# delay time

tWRD

—

12.5

Write data delay time

tWDD

—

12.5

Write data hold time

tWDH

0—

WAIT# setup time

tWTS

12.5

—

Figure 2.23

WAIT# hold time

tWTH

0—

Address delay time 2 (SDRAM)

tAD2

12.5

Figure 2.24 to

Figure 2.30

CS# delay time 2 (SDRAM)

tCSD2

12.5

DQM delay time (SDRAM)

tDQMD

12.5

CKE delay time (SDRAM)

tCKED

12.5

Read data setup time 2 (SDRAM)

tRDS2

—

Read data hold time 2 (SDRAM)

tRDH2

0—

Write data delay time 2 (SDRAM)

tWDD2

—

12.5

Write data hold time 2 (SDRAM)

tWDH2

1—

WE# delay time (SDRAM)

tWED

12.5

RAS# delay time (SDRAM)

tRASD

12.5

CAS# delay time (SDRAM)

tCASD

12.5

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