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74LVC1G79GS Datasheet(PDF) 9 Page - Nexperia B.V. All rights reserved |
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74LVC1G79GS Datasheet(HTML) 9 Page - Nexperia B.V. All rights reserved |
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9 / 21 page ![]() 74LVC1G79 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. Product data sheet Rev. 12 — 5 December 2016 9 of 21 NXP Semiconductors 74LVC1G79 Single D-type flip-flop; positive-edge trigger 12. Waveforms Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output. Fig 8. Clock (CP) to output (Q) propagation delay times Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output. Fig 9. Clock (CP) to output (Q) propagation delay times, clock pulse width, D to set-up times, the CP to D hold times and maximum clock pulse frequency |
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