PSD501B1 datasheet(88/153 Pages) STMICROELECTRONICS

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PSD5XX Family

Command Registers for Counter/Timers CMD0, CMD1, CMD2, CMD3 (Cont.)

Output Polarity Bit (3):

This bit is valid only in Waveform or Pulse mode and is

used to select the polarity of the Active output signal

of the Counter/Timer0. At RESET this bit initializes as 0

which means the Active output state is LOW. When this bit

is set to a

1: The Active output state is HIGH.

0: The Active output state is LOW.

Input Polarity Bit (4):

The state of this bit determines the polarity of the Active

input control signal to the Counter/Timer0 and is valid only

for input pin. At RESET this bit initializes as 0 which means

that the input Active is HIGH. When this bit is set to a

1: The input Active is LOW.

0: The input Active is HIGH.

Pin / PPLD Macrocell Bit (5): This bit determines whether the Counter/Timer0 gets its

input command for Load/Store and Enable/Disable from

the PSD5XX PIN or from the PPLD macrocell output.

At RESET this bit initializes as 0 which means that the

input command is coming from the PSD5XX PPLD

macrocell. When this bit is set to a

1: The Counter/Timer0 input command is coming from

the PIN.

0: The Counter/Timer0 input command is coming

from the PPLD macrocell output.

Software Gating Bit for

This bit gates the Load/Store command activated by the

Load/Store Commands (6):

PSD5XX PIN or PPLD macrocell. At RESET this bit

initializes as 0 which means that the Load/Store command

activated by the PIN or macrocell is permitted through.

When this bit is set to

1: Load/Store operation activated by PIN or Macrocell is

NOT permitted through.

0: Load/Store operation activated by PIN or macrocell is

permitted through. To further decide between the PIN

and PPLD macrocell, use bit 5 (PIN/PPLD macrocell).

Enable/Disable Using PIN,

This bit determines whether the Enable/Disable

PPLD Macrocell or Software command is activated by the PSD5XX Pin, PPLD macrocell

Bit (7):

or by Software. At RESET this bit initializes as 0, which

means that the Enable/Disable command is activated by

the PIN or PPLD macrocell. When this bit is set to

1: Enable/Disable command by PIN or macrocell is

overridden by Software (only Bit 2 of this register will

enable or disable the counter).

0: Enable/Disable command is activated by PIN or

Macrocell output. To further decide between the PIN and

PPLD macrocell use bit 5 (PIN / PPLD macrocell bit).

Counter/Timer

Registers

(Cont.)

PSD501B1 Datasheet(PDF) 88 Page - STMicroelectronics

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