PSD501B1 datasheet(29/153 Pages) STMICROELECTRONICS

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PSD5XX Family

9.1.3 The PPLD

The Peripheral Programmable Logic Device (PPLD) provides a powerful mechanism for

the user to control the operations of the Counter/Timer and Interrupt Controller. Figure 12 is

the PPLD block diagram. There are six Peripheral Macrocells, four are dedicated to the

Counter/Timer, and two to the Interrupt Controller.

The outputs from the four Peripheral Macrocells, MC2TMR[3:0], are used as

load/store/enable inputs to the Counter/Timer (multiplexed with pin inputs TIMER[3:0] _IN).

The remaining two macrocell outputs (MC2INT[6:7] ), together with two other product terms

(PT2INT4, PT2INT5), can generate up to 4 user defined interrupts to the Interrupt

Controller. The watch-dog output of the Timer (WDOG2PLD) and Interrupt Controller

(INTR2PLD) are available as inputs to the ZPLD’s AND ARRAY.

The structure of a Peripheral Macrocell is shown in Figure 13. The cell has two product term

inputs from the AND ARRAY. The user can select the registered or combinatorial output of

the macrocell, as well as the output polarity. The registers are clocked by the CLKIN clock,

and are cleared by the RESET input during power up.

9.1.4 The ZPLD Power Management

The ZPLD implements a Zero Power Mode, which provides considerable power savings

for low to medium frequency operations. To enable this feature, the ZPLD Turbo bit in the

Power Management Mode Register 0 (PMMR0) has to be turned off.

If none of the 61 inputs to the ZPLD are switching for a time period of 70ns, the ZPLD puts

itself into Zero Power Mode and the current consumption is minimal. The ZPLD will resume

normal operation as soon as one or more of the inputs change state.

Two other features of the ZPLD provide additional power savings:

1. Clock Disable:

Users can disable the clock input to the ZPLD and/or macrocells, thereby reducing AC

power consumption.

2. Product Term Disable:

Unused product terms in the ZPLD are disabled by the PSDsoft Software automatically

for further power savings.

The ZPLD power configuration is described in the Power Management Unit section.

The PSD5XX

Architecture

(cont.)

PSD501B1 Datasheet(PDF) 29 Page - STMicroelectronics