PSD501B1 datasheet(14/153 Pages) STMICROELECTRONICS

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PSD5XX Family

9.0

The PSD5XX

Architecture

PSD5XX consists of seven major functional blocks:

t ZPLD Blocks

t Bus Interface

t I/O Ports

t Memory Block

t Power Management Unit

t Counter/Timer

t Interrupt Controller

The functions of each block are described in the following sections. Many of the blocks

perform multiple functions, and are user configurable. The chip configurations are specified

by the user in the PSDsoft Development Software; some are specified by setting up the

appropriate bits in the configuration registers during run time.

9.1 ZPLD Block

Key Features

t 3 Embedded ZPLD devices

t Maximum 30 macrocells

t Combinatorial/registered outputs

t Maximum 140 product terms

t Programmable output polarity

t User configured register clear/preset

t User configured register clock input

t 61 Inputs

t Accessible via 24 I/O pins

t Power Saving Mode

t UV-Erasable

t Generate user defined interrupts to Interrupt Controller

and controls to Counter/ Timer

General Description

The ZPLD block has 3 embedded PLD devices:

t DPLD

The Address Decoding PLD, generating select signals to internal I/O or memory blocks.

t GPLD

The General Purpose PLD provides 24 programmable macrocells for general or

complex logic implementation; dedicated to user application.

t PPLD

The Peripheral PLD, includes 6 programmable macrocells. The PPLD provides control

to the operation of the Counter/Timer and Interrupt Controller.

Figure 4 shows the architecture of the ZPLD. The PLD devices all share the same

input bus. The true or complement of the 61 input signals are fed to the programmable

AND-ARRAY. Names and source of the input signals are shown in Table 3. The PA, PB, PE

signals, depending on user configuration, can either be macrocell feedbacks or inputs from

Port A, B or E.

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