Nexperia

PIMC32PAS-Q

50 V, 500 mA NPN/PNP Resistor-Equipped double Transistor; R1 = 2.2 kΩ, R2 = 10 kΩ

8. Limiting values

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

Max

Unit

Per transistor

VCBO

collector-base voltage

open emitter

[1]

-

50

V

VCEO

collector-emitter voltage open base

[1]

-

50

V

VEBO

emitter-base voltage

open collector

[1]

-

5

V

VI

input voltage

[1]

-5

12

V

IO

output current

[1]

-

500

mA

[2]

-

360

mW

[3]

-

550

mW

[4]

-

510

mW

Ptot

total power dissipation

Tamb ≤ 25 °C

[5]

-

730

mW

Per device

Tamb ≤ 25 °C

[2]

-

500

mW

[3]

-

750

mW

[4]

-

700

mW

Ptot

total power dissipation

[5]

-

1

W

Tj

junction temperature

-

150

°C

Tamb

ambient temperature

-55

150

°C

Tstg

storage temperature

-65

150

°C

[1] For the PNP transistor with negative polarity.

[2] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided, 35 µm copper, tin-plated and standard footprint.

[3] Device mounted on an FR4 PCB, single-sided, 35μm copper, tin-plated; mounting pad for collector 1 cm2.

[4] Device mounted on an FR4 PCB, 4-layer copper, tin-plated and standard footprint.

[5] Device mounted on an FR4 PCB, 4-layer copper, tin-plated; mounting pad for collector 1 cm2.

Tamb (°C)

-75

175

125

25

75

-25

aaa-037263

0.4

0.8

1.2

Ptot

(W)

0

(1)

(2)

(3)

(4)

(1) FR4 PCB, 4-layer copper, 1 cm2

(2) FR4 PCB, single-sided, 35μm copper, 1 cm2

(3) FR4 PCB, 4-layer copper, standard footprint

(4) FR4 PCB, single-sided, 35μm copper, standard footprint

Fig. 1. Per device: Power derating curves for DFN2020D-6 (SOT1118D)

PIMC32PAS-Q

All information provided in this document is subject to legal disclaimers.

© Nexperia B.V. 2023. All rights reserved

Product data sheet

31 August 2023

3 / 16