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NRF52810-QCAA-R7 Datasheet(PDF) 269 Page - Nordic Semiconductor |
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NRF52810-QCAA-R7 Datasheet(HTML) 269 Page - Nordic Semiconductor |
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269 / 483 page ![]() Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id RW Field Value Id Value Description A RW UPDOWN Selects up or up and down as wave counter mode Up 0 Up counter - edge aligned PWM duty-cycle UpAndDown 1 Up and down counter - center aligned PWM duty cycle 6.12.5.7 COUNTERTOP Address offset: 0x508 Value up to which the pulse generator counter counts Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A A A A A A A A A A A A A A A Reset 0x000003FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 Id RW Field Value Id Value Description A RW COUNTERTOP [3..32767] Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM will be used. 6.12.5.8 PRESCALER Address offset: 0x50C Configuration for PWM_CLK Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id RW Field Value Id Value Description A RW PRESCALER Pre-scaler of PWM_CLK DIV_1 0 Divide by 1 (16MHz) DIV_2 1 Divide by 2 ( 8MHz) DIV_4 2 Divide by 4 ( 4MHz) DIV_8 3 Divide by 8 ( 2MHz) DIV_16 4 Divide by 16 ( 1MHz) DIV_32 5 Divide by 32 ( 500kHz) DIV_64 6 Divide by 64 ( 250kHz) DIV_128 7 Divide by 128 ( 125kHz) 6.12.5.9 DECODER Address offset: 0x510 Configuration of the decoder 4430_161 v1.0 269 |
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