NRF52810-QCAA-R7 datasheet(372/483 Pages) NORDIC

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Peripherals

The SPIM does not implement support for chip select directly. Therefore, the CPU must use available

GPIOs to select the correct slave and control this independently of the SPI master. The SPIM supports SPI

modes 0 through 3. The CONFIG register allows setting CPOL and CPHA appropriately.

Mode

Clock polarity

Clock phase

CPOL

CPHA

SPI_MODE0

0 (Active High)

0 (Leading)

SPI_MODE1

0 (Active High)

1 (Trailing)

SPI_MODE2

1 (Active Low)

0 (Leading)

SPI_MODE3

1 (Active Low)

1 (Trailing)

Table 73: SPI modes

6.18.1 SPI master transaction sequence

An SPI master transaction consists of a sequence started by the START task followed by a number of

events, and finally the STOP task.

An SPI master transaction is started by triggering the START task. The ENDTX event will be generated when

the transmitter has transmitted all bytes in the TXD buffer as specified in the TXD.MAXCNT register. The

ENDRX event will be generated when the receiver has filled the RXD buffer, i.e. received the last possible

byte as specified in the RXD.MAXCNT register.

Following a START task, the SPI master will generate an END event when both ENDRX and ENDTX have

been generated.

The SPI master is stopped by triggering the STOP task. A STOPPED event is generated when the SPI master

has stopped.

If the ENDRX event has not already been generated when the SPI master has come to a stop, the SPI

master will generate the ENDRX event explicitly even though the RX buffer is not full.

If the ENDTX event has not already been generated when the SPI master has come to a stop, the SPI

master will generate the ENDTX event explicitly even though all bytes in the TXD buffer, as specified in the

TXD.MAXCNT register, have not been transmitted.

The SPI master is a synchronous interface, and for every byte that is sent, a different byte will be received

at the same time; this is illustrated in SPI master transaction on page 373.

4430_161 v1.0

372

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