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NRF52810-QFAA-R Datasheet(PDF) 388 Page - Nordic Semiconductor |
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NRF52810-QFAA-R Datasheet(HTML) 388 Page - Nordic Semiconductor |
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388 / 483 page ![]() Peripherals 6.19.5.3 INTENCLR Address offset: 0x308 Disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id C B A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id RW Field Value Id Value Description A RW END Write '1' to Disable interrupt for END event See EVENTS_END Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled B RW ENDRX Write '1' to Disable interrupt for ENDRX event See EVENTS_ENDRX Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled C RW ACQUIRED Write '1' to Disable interrupt for ACQUIRED event See EVENTS_ACQUIRED Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled 6.19.5.4 SEMSTAT Address offset: 0x400 Semaphore status register Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A A Reset 0x00000001 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Id RW Field Value Id Value Description A R SEMSTAT Semaphore status Free 0 Semaphore is free CPU 1 Semaphore is assigned to CPU SPIS 2 Semaphore is assigned to SPI slave CPUPending 3 Semaphore is assigned to SPI but a handover to the CPU is pending 6.19.5.5 STATUS Address offset: 0x440 Status from last transaction Individual bits are cleared by writing a '1' to the bits that shall be cleared 4430_161 v1.0 388 |
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