NRF52810-QFAA-R datasheet(18/483 Pages) NORDIC

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Core components

Base Address

Peripheral

Instance

Description

0x40015000

EGU

EGU1

Event generator unit 1

0x40015000

SWI

SWI1

Software interrupt 1

0x40016000

SWI

SWI2

Software interrupt 2

0x40017000

SWI

SWI3

Software interrupt 3

0x40018000

SWI

SWI4

Software interrupt 4

0x40019000

SWI

SWI5

Software interrupt 5

0x4001C000

PWM

PWM0

Pulse-width modulation unit 0

0x4001D000

PDM

Pulse-density modulation (digital microphone interface)

0x4001E000

NVMC

Non-volatile memory controller

0x4001F000

PPI

Programmable peripheral interconnect

0x50000000

GPIO

General purpose input and output

N/A

0x10000000

FICR

Factory information configuration

N/A

0x10001000

UICR

User information configuration

Table 4: Instantiation table

4.3 NVMC — Non-volatile memory controller

The non-volatile memory controller (NVMC) is used for writing and erasing of the internal flash memory

and the UICR (user information configuration registers).

The CONFIG register is used to enable the NVMC for writing (CONFIG.WEN) and erasing (CONFIG.EEN), see

CONFIG on page 19. The user must make sure that writing and erasing are not enabled at the same

time. Having both enabled at the same time may result in unpredictable behavior.

4.3.1 Writing to flash

When writing is enabled, full 32-bit words are written to word-aligned addresses in flash.

As illustrated in Memory on page 15, the flash is divided into multiple pages that in turn are divided

into multiple blocks. The same block in flash can only be written nWRITE number of times before an erase

must be performed using ERASEPAGE or ERASEALL. See the memory size and organization in Memory on

page 15 for block size.

The NVMC is only able to write

0 to bits in the flash that are erased (set to 1). It cannot rewrite a bit back

1. Only full 32-bit words can be written to flash using the NVMC interface. To write less than 32 bits,

write the data as a full 32-bit word and set all the bits that should remain unchanged in the word to

Note that the restriction on the number of writes (nWRITE) still applies in this case.

Only word-aligned writes are allowed. Byte or half-word-aligned writes will result in a hard fault.

The time it takes to write a word to flash is specified by tWRITE. The CPU is halted if the CPU executes code

from the flash while the NVMC is writing to the flash.

4.3.2 Erasing a page in flash

When erase is enabled, the flash memory can be erased page by page using the ERASEPAGE register.

After erasing a flash page, all bits in the page are set to

1. The time it takes to erase a page is specified

by tERASEPAGE. The CPU is halted if the CPU executes code from the flash while the NVMC is writing to the

flash.

4.3.3 Writing to user information configuration registers (UICR)

User information configuration registers (UICR) are written in the same way as flash. After UICR has been

written, the new UICR configuration will take effect after a reset.

4430_161 v1.0

NRF52810-QFAA-R Datasheet(PDF) 18 Page - Nordic Semiconductor

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