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NRF52810-QFAA-R Datasheet(PDF) 16 Page - Nordic Semiconductor

Part # NRF52810-QFAA-R
Description  RF52810
PDF  483 Pages
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Manufacturer  NORDIC [Nordic Semiconductor]
Direct Link  https://www.nordicsemi.com/
Logo NORDIC - Nordic Semiconductor

NRF52810-QFAA-R Datasheet(HTML) 16 Page - Nordic Semiconductor

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Core components
0x20000000
0x20001000
0x20002000
0x20003000
0x20004000
0x20005000
RAM2
AHB slave
RAM1
AHB slave
RAM0
AHB slave
Section 0
Section 1
Section 0
Section 1
Section 0
Section 1
AHB multilayer interconnect
Data RAM
System
Page 0
Page 1
Page 2
Page 3..46
Page 47
0x00000000
0x00002000
0x00003000
0x0002F000
Flash
ICODE/DCODE
ICODE
DCODE
0x00800000
0x00801000
0x00802000
0x00803000
0x00804000
0x00805000
Code RAM
ICODE/DCODE
Peripheral
EasyDMA
Peripheral
EasyDMA
CPU
ARM Cortex-M4
AHB2APB
AHB
APB
Block 0
Block 1
Block 2..6
Block 7
0x00000200
0x00000400
0x00001000
0x00000E00
Figure 2: Memory layout
See AHB multilayer on page 50 and EasyDMA on page 48 for more information about the AHB
multilayer interconnect and the EasyDMA.
The same physical RAM is mapped to both the Data RAM region and the Code RAM region. It is up to the
application to partition the RAM within these regions so that one does not corrupt the other.
4.2.1 RAM - Random access memory
The RAM interface is divided into multiple RAM AHB slaves.
Each RAM AHB slave is connected to two 4-kilobyte RAM sections, see Section 0 and Section 1 in Memory
layout on page 16.
Each of the RAM sections have separate power control for System ON and System OFF mode operation,
which is configured via RAM register (see the POWER — Power supply on page 61).
4.2.2 Flash - Non-volatile memory
The flash can be read an unlimited number of times by the CPU, but it has restrictions on the number of
times it can be written and erased, and also on how it can be written.
Writing to flash is managed by the non-volatile memory controller (NVMC), see NVMC — Non-volatile
memory controller on page 18.
The flash is divided into multiple 4 kB pages that can be accessed by the CPU via both the ICODE and
DCODE buses as shown in, Memory layout on page 16. Each page is divided into 8 blocks.
4.2.3 Memory map
The complete memory map is shown in Memory map on page 17. As described in Memory on page
15, Code RAM and Data RAM are the same physical RAM.
4430_161 v1.0
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