NRF52810-QFAA-R datasheet(404/483 Pages) NORDIC

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Peripherals

In Timer mode, the TIMER's internal Counter register is incremented by one for every tick of the timer

frequency fTIMER as illustrated in Block schematic for timer/counter on page 403. The timer frequency is

derived from PCLK16M as shown below, using the values specified in the PRESCALER register:

fTIMER = 16 MHz / (2PRESCALER)

When fTIMER <= 1 MHz the TIMER will use PCLK1M instead of PCLK16M for reduced power consumption.

In counter mode, the TIMER's internal Counter register is incremented by one each time the COUNT task

is triggered, that is, the timer frequency and the prescaler are not utilized in counter mode. Similarly, the

COUNT task has no effect in Timer mode.

The TIMER's maximum value is configured by changing the bit-width of the timer in the BITMODE on

page 408 register.

PRESCALER on page 409 and the BITMODE on page 408 must only be updated when the timer is

stopped. If these registers are updated while the TIMER is started then this may result in unpredictable

behavior.

When the timer is incremented beyond its maximum value the Counter register will overflow and the

TIMER will automatically start over from zero.

The Counter register can be cleared, that is, its internal value set to zero explicitly, by triggering the CLEAR

task.

The TIMER implements multiple capture/compare registers.

Independent of prescaler setting the accuracy of the TIMER is equivalent to one tick of the timer

frequency fTIMER as illustrated in Block schematic for timer/counter on page 403.

6.22.1 Capture

The TIMER implements one capture task for every available capture/compare register.

Every time the CAPTURE[n] task is triggered, the Counter value is copied to the CC[n] register.

6.22.2 Compare

The TIMER implements one COMPARE event for every available capture/compare register.

A COMPARE event is generated when the Counter is incremented and then becomes equal to the

value specified in one of the capture compare registers. When the Counter value becomes equal to the

value specified in a capture compare register CC[n], the corresponding compare event COMPARE[n] is

generated.

BITMODE on page 408 specifies how many bits of the Counter register and the capture/compare

6.22.3 Task delays

After the TIMER is started, the CLEAR task, COUNT task and the STOP task will guarantee to take effect

within one clock cycle of the PCLK16M.

6.22.4 Task priority

If the START task and the STOP task are triggered at the same time, that is, within the same period of

PCLK16M, the STOP task will be prioritized.

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NRF52810-QFAA-R Datasheet(PDF) 404 Page - Nordic Semiconductor