NRF52810-QFAA-R datasheet(412/483 Pages) NORDIC

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Peripherals

A typical TWI setup consists of one master and one or more slaves. For an example, see A typical TWI

setup comprising one master and three slaves on page 412. This TWIM is only able to operate as a

single master on the TWI bus. Multi-master bus configuration is not supported.

TWI master

(TWIM)

TWI slave

(Sensor)

Address = b1011000

TWI slave

Address = b1011011

SCL

TWI slave

(EEPROM)

Address = b1011001

SCL

VDD

SDA

SCL

SDA

Figure 107: A typical TWI setup comprising one master and three slaves

This TWI master supports clock stretching performed by the slaves. Note that the SCK pulse following a

stretched clock cycle may be shorter than specified by the I2C specification.

The TWI master is started by triggering the STARTTX or STARTRX tasks, and stopped by triggering the STOP

task. The TWI master will generate a STOPPED event when it has stopped following a STOP task. The TWI

master cannot get stopped while it is suspended, so the STOP task has to be issued after the TWI master

has been resumed.

After the TWI master is started, the STARTTX task or the STARTRX task should not be triggered again

before the TWI master has stopped, i.e. following a LASTRX, LASTTX or STOPPED event.

If a NACK is clocked in from the slave, the TWI master will generate an ERROR event.

6.23.1 EasyDMA

The TWI master implements EasyDMA for reading and writing to and from the RAM.

If the TXD.PTR and the RXD.PTR are not pointing to the Data RAM region, an EasyDMA transfer may result

in a HardFault or RAM corruption. See Memory on page 15 for more information about the different

memory regions.

The .PTR and .MAXCNT registers are double-buffered. They can be updated and prepared for the next RX/

TX transmission immediately after having received the RXSTARTED/TXSTARTED event.

The STOPPED event indicates that EasyDMA has finished accessing the buffer in RAM.

6.23.2 Master write sequence

A TWI master write sequence is started by triggering the STARTTX task. After the STARTTX task has been

triggered, the TWI master will generate a start condition on the TWI bus, followed by clocking out the

address and the READ/WRITE bit set to 0 (WRITE=0, READ=1).

The address must match the address of the slave device that the master wants to write to. The READ/

WRITE bit is followed by an ACK/NACK bit (ACK=0 or NACK=1) generated by the slave.

After receiving the ACK bit, the TWI master will clock out the data bytes found in the transmit buffer

located in RAM at the address specified in the TXD.PTR register. Each byte clocked out from the master will

be followed by an ACK/NACK bit clocked in from the slave.

A typical TWI master write sequence is illustrated in TWI master writing data to a slave on page 413.

Occurrence 2 in the figure illustrates clock stretching performed by the TWI master following a SUSPEND

task.

A SUSPENDED event indicates that the SUSPEND task has taken effect; this event can be used to

synchronize the software.

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