NRF52810-QFAA-R datasheet(138/483 Pages) NORDIC

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Peripherals

When the correct level is detected on any such configured pin, the sense mechanism will set the DETECT

signal high. Each pin has a separate DETECT signal. Default behavior, defined by the DETECTMODE register,

is that the DETECT signals from all pins in the GPIO port are combined into one common DETECT signal

that is routed throughout the system, which then can be utilized by other peripherals. This mechanism

is functional in both System ON mode and System OFF mode. See GPIO port and the GPIO pin details on

page 138.

GPIO port

PIN31

PIN0

PIN31

PIN[31].CNF

PIN[31].IN

PIN[31].OUT

PIN0

PIN[0].CNF

PIN[0].IN

PIN[0].OUT

PIN0

PIN[0].OUT

PIN[0].IN

Sense

OUT_OVERRIDE

DIR_OVERRIDE

PIN0.DETECT

OUT

O: output buffer

I: input buffer

PIN[0].CNF.INPUT

PIN[0].CNF.PULL

PIN[0].CNF.DRIVE

PIN[0].CNF.SENSE

PIN[0].CNF.DIR

INPUT_OVERRIDE

ANAIN

ANAEN

PIN1.DETECT

PIN31.DETECT

LATCH

LDETECT

DETECT

DETECTMODE

Figure 39: GPIO port and the GPIO pin details

GPIO port and the GPIO pin details on page 138 illustrates the GPIO port containing 32 individual pins,

where

PIN0 is illustrated in more detail as a reference. All signals on the left side in the illustration are

used by other peripherals in the system and therefore not directly available to the CPU.

Make sure that a pin is in a level that cannot trigger the sense mechanism before enabling it. The DETECT

signal will go high immediately if the SENSE condition configured in the PIN_CNF registers is met when the

sense mechanism is enabled. This will trigger a PORT event if the DETECT signal was low before enabling

the sense mechanism. See GPIOTE — GPIO tasks and events on page 188.

See the following peripherals for more information about how the DETECT signal is used:

• POWER: uses the DETECT signal to exit from System OFF mode.

• GPIOTE: uses the DETECT signal to generate the PORT event.

When a pin's PINx.DETECT signal goes high, a flag will be set in the LATCH register. For example, when

the PIN0.DETECT signal goes high, bit 0 in the LATCH register will be set to '1'. If the CPU performs a clear

operation on a bit in the LATCH register when the associated PINx.DETECT signal is high, the bit in the

LATCH register will not be cleared. The LATCH register will only be cleared if the CPU explicitly clears it by

writing a '1' to the bit that shall be cleared, i.e. the LATCH register will not be affected by a PINx.DETECT

signal being set low.

The LDETECT signal will be set high when one or more bits in the LATCH register are '1'. The LDETECT signal

will be set low when all bits in the LATCH register are successfully cleared to '0'.

If one or more bits in the LATCH register are '1' after the CPU has performed a clear operation on the

LATCH registers, a rising edge will be generated on the LDETECT signal. This is illustrated in DETECT signal

behavior on page 139.

Important: The CPU can read the LATCH register at any time to check if a SENSE condition has been

met on one or more of the the GPIO pins, even if that condition is no longer met at the time the

CPU queries the LATCH register. This mechanism will work even if the LDETECT signal is not used as

the DETECT signal.

The LDETECT signal is by default not connected to the GPIO port's DETECT signal, but via the DETECTMODE

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NRF52810-QFAA-R Datasheet(PDF) 138 Page - Nordic Semiconductor

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