NRF52811-QCAA-R7 datasheet(382/444 Pages) NORDIC

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Peripherals

If flow control is enabled a transmission will be automatically suspended when CTS is deactivated and

resumed when CTS is activated again, as illustrated in UART transmission on page 382. A byte that is in

transmission when CTS is deactivated will be fully transmitted before the transmission is suspended. For

more information, see Suspending the UART on page 383.

N-1

N-2

Figure 145: UART transmission

6.27.5 Reception

A UART reception sequence is started by triggering the STARTRX task.

The UART receiver chain implements a FIFO capable of storing six incoming RXD bytes before data is

overwritten. Bytes are extracted from this FIFO by reading the RXD register. When a byte is extracted from

the FIFO a new byte pending in the FIFO will be moved to the RXD register. The UART will generate an

RXDRDY event every time a new byte is moved to the RXD register.

When flow control is enabled, the UART will deactivate the RTS signal when there is only space for four

more bytes in the receiver FIFO. The counterpart transmitter is therefore able to send up to four bytes

after the RTS signal is deactivated before data is being overwritten. To prevent overwriting data in the

FIFO, the counterpart UART transmitter must therefore make sure to stop transmitting data within four

bytes after the RTS line is deactivated.

The RTS signal will first be activated again when the FIFO has been emptied, that is, when all bytes in the

FIFO have been read by the CPU, see UART reception on page 383.

The RTS signal will also be deactivated when the receiver is stopped through the STOPRX task as illustrated

in UART reception on page 383. The UART is able to receive four to five additional bytes if they are sent

in succession immediately after the RTS signal has been deactivated. This is possible because the UART is,

even after the STOPRX task is triggered, able to receive bytes for an extended period of time dependent

on the configured baud rate. The UART will generate a receiver timeout event (RXTO) when this period has

elapsed.

To prevent loss of incoming data the RXD register must only be read one time following every RXDRDY

event.

To secure that the CPU can detect all incoming RXDRDY events through the RXDRDY event register, the

RXDRDY event register must be cleared before the RXD register is read. The reason for this is that the

UART is allowed to write a new byte to the RXD register, and therefore can also generate a new event,

immediately after the RXD register is read (emptied) by the CPU.

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NRF52811-QCAA-R7 Datasheet(PDF) 382 Page - Nordic Semiconductor