NRF52811-QCAA-R7 datasheet(305/444 Pages) NORDIC

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Peripherals

The semaphore mechanism does not, at any time, prevent the CPU from performing read or write access

to the RXD.PTR register, the TXD.PTR registers, or the RAM that these pointers are pointing to. The

semaphore is only telling when these can be updated by the CPU so that safe sharing is achieved.

The semaphore is by default assigned to the CPU after the SPI slave is enabled. No ACQUIRED event will be

generated for this initial semaphore handover. An ACQUIRED event will be generated immediately if the

ACQUIRE task is triggered while the semaphore is assigned to the CPU.

The SPI slave will try to acquire the semaphore when CSN goes low. If the SPI slave does not manage to

acquire the semaphore at this point, the transaction will be ignored. This means that all incoming data on

MOSI will be discarded, and the DEF (default) character will be clocked out on the MISO line throughout

the whole transaction. This will also be the case even if the semaphore is released by the CPU during the

transaction. In case of a race condition where the CPU and the SPI slave try to acquire the semaphore at

the same time, as illustrated in lifeline item 2 in SPI transaction when shortcut between END and ACQUIRE

is enabled on page 306, the semaphore will be granted to the CPU.

If the SPI slave acquires the semaphore, the transaction will be granted. The incoming data on MOSI will

be stored in the RXD buffer and the data in the TXD buffer will be clocked out on MISO.

When a granted transaction is completed and CSN goes high, the SPI slave will automatically release the

semaphore and generate the END event.

As long as the semaphore is available the SPI slave can be granted multiple transactions one after the

other. If the CPU is not able to reconfigure the TXD.PTR and RXD.PTR between granted transactions, the

same TX data will be clocked out and the RX buffers will be overwritten. To prevent this from happening,

the END_ACQUIRE shortcut can be used. With this shortcut enabled the semaphore will be handed over

to the CPU automatically after the granted transaction has completed, giving the CPU the ability to update

the TXPTR and RXPTR between every granted transaction.

If the CPU tries to acquire the semaphore while it is assigned to the SPI slave, an immediate handover

will not be granted. However, the semaphore will be handed over to the CPU as soon as the SPI slave

has released the semaphore after the granted transaction is completed. If the END_ACQUIRE shortcut

is enabled and the CPU has triggered the ACQUIRE task during a granted transaction, only one ACQUIRE

request will be served following the END event.

The MAXRX register specifies the maximum number of bytes the SPI slave can receive in one granted

transaction. If the SPI slave receives more than MAXRX number of bytes, an OVERFLOW will be indicated

in the STATUS register and the incoming bytes will be discarded.

The MAXTX parameter specifies the maximum number of bytes the SPI slave can transmit in one granted

transaction. If the SPI slave is forced to transmit more than MAXTX number of bytes, an OVERREAD will be

indicated in the STATUS register and the ORC character will be clocked out.

The RXD.AMOUNT and TXD.AMOUNT registers are updated when a granted transaction is completed.

The TXD.AMOUNT register indicates how many bytes were read from the TX buffer in the last transaction,

that is, ORC (over-read) characters are not included in this number. Similarly, the RXD.AMOUNT register

indicates how many bytes were written into the RX buffer in the last transaction.

The ENDRX event is generated when the RX buffer has been filled.

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NRF52811-QCAA-R7 Datasheet(PDF) 305 Page - Nordic Semiconductor

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