NRF52811-QCAA-R7 datasheet(328/444 Pages) NORDIC

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Peripherals

as long as the TWI master is enabled, and retained only as long as the device is in ON mode. PSEL.SCL and

PSEL.SDA must only be configured when the TWI is disabled.

To secure correct signal levels on the pins used by the TWI master when the system is in OFF mode, and

when the TWI master is disabled, these pins must be configured in the GPIO peripheral as described in

GPIO configuration on page 328.

Only one peripheral can be assigned to drive a particular GPIO pin at a time, failing to do so may result in

unpredictable behavior.

TWI master signal

TWI master pin

Direction

Drive strength

Output value

SCL

As specified in PSEL.SCL

Input

S0D1

Not applicable

SDA

As specified in PSEL.SDA

Input

S0D1

Not applicable

Table 98: GPIO configuration

6.23.3 Shared resources

The TWI shares registers and other resources with other peripherals that have the same ID as the TWI.

Therefore, you must disable all peripherals that have the same ID as the TWI before the TWI can be

configured and used. Disabling a peripheral that has the same ID as the TWI will not reset any of the

registers that are shared with the TWI. It is therefore important to configure all relevant TWI registers

explicitly to secure that it operates correctly.

The Instantiation table in Instantiation on page 18 shows which peripherals have the same ID as the TWI.

6.23.4 Master write sequence

A TWI master write sequence is started by triggering the STARTTX task. After the STARTTX task has been

triggered, the TWI master will generate a start condition on the TWI bus, followed by clocking out the

address and the READ/WRITE bit set to 0 (WRITE=0, READ=1).

The address must match the address of the slave device that the master wants to write to. The READ/

WRITE bit is followed by an ACK/NACK bit (ACK=0 or NACK=1) generated by the slave.

After receiving the ACK bit, the TWI master will clock out the data bytes that are written to the TXD

slave. A TXDSENT event will be generated each time the TWI master has clocked out a TXD byte, and the

associated ACK/NACK bit has been clocked in from the slave.

The TWI master transmitter is single buffered, and a second byte can only be written to the TXD register

after the previous byte has been clocked out and the ACK/NACK bit clocked in, that is, after the TXDSENT

event has been generated.

If the CPU is prevented from writing to TXD when the TWI master is ready to clock out a byte, the TWI

master will stretch the clock until the CPU has written a byte to the TXD register.

A typical TWI master write sequence is illustrated in The TWI master writing data to a slave on page

329. Occurrence 3 in the figure illustrates delayed processing of the TXDSENT event associated with

TXD byte 1. In this scenario the TWI master will stretch the clock to prevent writing erroneous data to the

slave.

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