NRF52811-QCAA-R7 datasheet(368/444 Pages) NORDIC

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Peripherals

When the write command is received the TWI slave will enter the RX state if the internal 'RX prepared' flag

is set.

If the internal 'RX prepared' flag is not set when the write command is received, the TWI slave will stretch

the master's clock until the PREPARERX task is triggered and the internal 'RX prepared' flag is set.

The TWI slave will generate the RXSTARTED event and clear the internal 'RX prepared' flag ('unprepare RX')

when it enters the RX state. In this state the TWI slave will be able to receive the bytes sent by the TWI

master. The TWI slave will consume IRX in this mode.

The TWI slave will go back to the IDLE state if the TWI slave receives a restart command when it is in the

RX state.

The TWI slave is stopped when it receives the stop condition from the TWI master. A STOPPED event will

be generated when the transaction has stopped. The TWI slave will clear the internal 'RX prepared' flag

('unprepare RX') and go back to the IDLE state when it has stopped.

The receive buffer is located in RAM at the address specified in the TXD.PTR register. The TWI slave will

only be able to receive as many bytes as specified in the RXD.MAXCNT register. If the TWI master tries to

send more bytes to the slave than the slave is able to receive,these bytes will be discarded and the bytes

will be NACKed by the slave. If this happens, an ERROR event will be generated.

The EasyDMA configuration registers, see RXD.PTR etc., are latched when the RXSTARTED event is

generated.

The TWI slave can be forced to stop by triggering the STOP task. A STOPPED event will be generated when

the TWI slave has stopped. The TWI slave will clear the internal 'RX prepared' flag and go back to the IDLE

state when it has stopped, see also Terminating an ongoing TWI transaction on page 369.

The TWI slave will generate an ACK after every byte received from the master. The RXD.AMOUNT register

can be queried after a transaction to see how many bytes were received.

A typical TWI slave write command response is illustrated in The TWI slave responding to a write

command on page 368. Occurrence 2 in the figure illustrates clock stretching performed by the TWI

slave following a SUSPEND task.

ADDR

M-1

Stretch

Figure 141: The TWI slave responding to a write command

6.26.4 Master repeated start sequence

An example of a repeated start sequence is one in which the TWI master writes two bytes to the slave

followed by reading four bytes from the slave.

This is illustrated in A repeated start sequence, where the TWI master writes two bytes followed by

reading four bytes from the slave on page 369.

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NRF52811-QCAA-R7 Datasheet(PDF) 368 Page - Nordic Semiconductor