RMLD232UAW datasheet(17/50 Pages) EMLSI

17 / 50 page

Rev 0.7

64Mb Low Power DDR SDRAM

Advanced

Write Interrupted by a Precharge & DM

A burst write operation can be interrupted before completion of the burst by a precharge of the same bank. Random column access is

allowed. A write recovery time(tWR) is required from the last data to precharge command. When precharge command is asserted, any

residual data from the burst write cycle must be masked by DM.

Precharge timing for Write operations in DRAMs requries enough time to allow “write recovery “ which is the time required by a

DRAM core to properly store a full “0” or “1” level before a Precharge operation. For DDR SDRAM, a timing parameter, tWR, is used

to indicate the required amount of time between the last valid write operation and a Precharge command to the same bank.

The precharge timing for writes is a complex definition since the write data is sampled by the data strobe and the address is sampled

by the input clock. Inside the SDRAM, the data path is eventually synchronized with the address path by swithing clock domains from

the data strobe clock domain to the input clock domain. This makes the definition of when a precharge operation can be initiated after

a write very complex since the write recovery parameter must reference only the clock domain that is used to time the internal write

operation, i.e., the input clock domain.

tWR starts on the rising clock edge after the last possible DQS edge that strobed in the last valid data and ends on the rising clok edge

that strobes in the prechrge command.

1. For the earilest possible Precharge command following a Write burst without interrupting the burst , the minimum time for write

recovery is defined by tWR.

2. When a precharge command interrupts a Write burst operation, the data mask pin, DM, is used to mask input data during the time

between the last valid write data and the rising clock edge on which the Precharge command is given. During this time, the DQS

input is still required to strobe in the state of DM. The minimum time for write recovery is defined by tWR.

3. For a Write with autoprecharge command, a new Bank Activate command may be issued to the same bank after tWR+tRP where

tWR+tRP starts on the falling DQS edge that strobed in the last valid data and ends on the rising clock edge that strobes in the Bank

Activate command. During write with autoprecharge, the initiation of the internal precharge occurs at the same time as the earliest

possible external Precharge command without interrupting the Write burst as described in 1 above.

4. In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to Precharge time] has been

satisfied. This includes Write with autoprecharge commands where tRAS(min) must still be satisfied such that a Write with

autoprecharge command has the same timing as a Write command followed by the earliest possible Precharge command which

does not interrupt the burst.

5. Refer to “3.3.2 Burst write operation”

Command

NOP

Precharge

DQS

DQs

Figure.11 Write interrupted by a precharge and DM timing

< Burst Length=8 >

WRITE A

Din a0

NOP

WRITE B

Din a1 Din a2 Din a3 Din a4 Din a5

NOP

Din a0 Din a1 Din a2 Din a3 Din a4 Din a5

Din a6 Din a7

Din b0 Din b1

Din b0 Din b1 Din b2

Din a6 Din a7

Min tDQSS

DQS

DQs

Max tDQSS

tDQSSmax

tWPRES tWPREH

tDQSSmin

tWPRES tWPREH

tDQSSmax

tDQSSmin

tWPRES tWPREH

tWR

RMLD232UAW Datasheet(PDF) 17 Page - Emerging Memory & Logic Solutions Inc

RMLD232UAW Datasheet(HTML) 17 Page - Emerging Memory & Logic Solutions Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Datasheet Download

Link URL