RMLD232UAW datasheet(18/50 Pages) EMLSI

18 / 50 page

Rev 0.7

64Mb Low Power DDR SDRAM

Advanced

Burst Stop

The burst stop command is initiated by having RAS and CAS high with CS and WE low at the rising edge of the clock(CK). The burst

stop command has the fewest restrictions making it the easiest method to use when terminating a burst read operation before it has

been completed. When the burst stop command is issued during a burst read cycle, the pair of data and DQS(Data Strobe) go to a

high impedance state after a delay which is equal to the CAS latency set in the mode register. The burst stop command, however, is

not supported during a write burst operation.

The Burst Stop command is a mandatory feature for DDR SDRAMs. The following functionality is required:

1. The BST command may only be issued on the rising edge of the onput clock, CK.

2. BST is only a valid command during Read bursts.

3. BST during a Write burst is undefined and shall not be used.

4. BST applies to all burst lengths.

5. BST is an undefined command during Read with autoprecharge and shall not be used.

6. When terminating a burst Read command, the BST command must be issued LBST(“BST Latency”) clock cycles before the clock

edge at which the output buffers are tristated, where LBST equals the CAS latency for read operations.

7. When the burst terminates, the DQ and DQS pins are tristated.

The BST command is not byte controllable and applies to all bits in the DQ data word and the(all) DQS pin(s).

Command

NOP

DQS

DQs

Figure.12 Burst stop timing

< Burst Length=4, CAS Latency=3 >

Burst Stop

Dout 0

NOP

READ A

NOP

Dout 1

NOP

The burst read ends after a delay equal to the CAS latency.

CAS Latency=3

RMLD232UAW Datasheet(PDF) 18 Page - Emerging Memory & Logic Solutions Inc