| Electronic Components Datasheet Search |
|
RMLD232UAW Datasheet(PDF) 36 Page - Emerging Memory & Logic Solutions Inc |
|
|
|||||||||||||||||||||||||||||
RMLD232UAW Datasheet(HTML) 36 Page - Emerging Memory & Logic Solutions Inc |
|
36 / 50 page ![]() 36 Rev 0.7 64Mb Low Power DDR SDRAM Advanced AC Operating Test Conditions (VDD = 1.7V - 1.95V, TA = -25 to 85 ) Input/Output Capacitance (VDD=1.8V, VDDQ=1.8V, TA=25 , f=1 ) Parameter Value Unit AC input levels(Vih/Vil) 0.8 VDDQ / 0.2 VDDQ V Input timing measurement reference level 0.5 VDDQ V Input signal minimum slew rate 1.0 V/ Output timing measurement reference level 0.5 VDDQ V Output load condition See Figure 2 Parameter Symbol Min Max Unit Input capacitance (A0 ~ A11, BA0 ~ BA1, CKE, CS, RAS, CAS, WE) CIN1 1.5 3.0 Input capacitance(CK, CK) CIN2 1.5 3.5 Data & DQS input/output capacitance COUT 2.0 4.5 Input capacitance(DM) CIN3 2.0 4.5 1.8V 13.9 VOH (DC) =0.9 VDDQ, IOH = -0.1 VOL (DC) =0.1 VDDQ , IOL = 0.1 20 Z0=50 Vtt=0.5 VDDQ 50 20 (Full DS) Figure 1. DC Output Load Circuit Figure 2. AC Output Load Circuit Output Output 10.6 10 (Half DS) CL 5 (Quarter DS) 2.5 (Octant DS) |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |