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EMC646SP16JS-85LL Datasheet(PDF) 27 Page - Emerging Memory & Logic Solutions Inc |
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EMC646SP16JS-85LL Datasheet(HTML) 27 Page - Emerging Memory & Logic Solutions Inc |
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27 / 65 page ![]() EMC646SP16J 4Mx16 CellularRAM 27 Preliminary Refresh Configuration Register The refresh configuration register (RCR) defines how the CellularRAM device performs its transparent self refresh. Altering the refresh parameters can dramatically reduce current consumption during standby mode. Page mode control is also embedded into the RCR. Fig- ure 20 describes the control bits used in the RCR. At power-up, the RCR is set to 0010h. The RCR is accessed with CRE HIGH and A[19:18] = 00b; or through the register access software sequence with DQ = 0000h on the third cycle. Figure 20: Refresh Configuration Register Mapping Address Bus A[21:20] A[19:18] A[17:8] A7 A6 A5 A4 A3 A2 A1 A0 21-20 19-18 17-8 7 6 5 4 3 2 1 0 Reserved Register Select Reserved Page Reserved DPD Reserved PAR RCR[19] RCR[18] Register Select RCR[2] RCR[1] RCR[0] Refresh Coverage 0 0 Select RCR 0 0 0 Full array (default) 1 0 Select BCR 0 0 1 Bottom 1/2 array 0 1 Select DIDR 0 1 0 Bottom 1/4 array 0 1 1 Bottom 1/8 array 1 0 0 None of array RCR[7] Page Mode Enable/Disable 1 0 1 Top 1/2 array 0 Page Mode Disable (default) 1 1 0 Top 1/4 array 1 Page Mode Enable 1 1 1 Top 1/8 array RCR[4] Deep Power-Down 0 DPD Enable 1 DPD Disable (default) All must be All must be Setting is ignored Must be set to “0” (Default 00b) set to “0” set to “0” |
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