EMC646SP16JS-85LL datasheet(52/65 Pages) EMLSI

52 / 65 page

EMC646SP16J

4Mx16 CellularRAM

Preliminary

Figure 41. Burst WRITE Followed by Burst READ

Note:

1. Non-default BCR settings for burst WRITE followed by burst READ: Fixed or variable latency; latency code two (three clocks); WAIT active LOW;

WAIT asserted during delay.

2. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE#

HIGH, or b) CE# HIGH for longer than 15ns. CE# can stay LOW between burst READ and burst WRITE operations, but CE# must not remain

LOW longer than tCEM. See burst interrupt diagrams for cases where CE# stays LOW between bursts.

CLK

ADV#

CE#

OE#

WAIT

DQ[15:0]

Don’t Care

Undefined

A[21:0]

LB#/UB#

VIH

VIL

WE#

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VIH

VIL

Note 2

Valid

Address

tCLK

Valid

Output

tCSP

VOH

VOL

tSP tHD

Valid

Address

tSP tHD

tCSP

tSP tHD

Valid

Output

Valid

Output

Valid

Output

tSP tHD

tCBPH

tHD

tOHZ

tSP tHD

tBOE

tACLK

tKOH

tSP

tHD

High-Z

IN/OUT

EMC646SP16JS-85LL Datasheet(PDF) 52 Page - Emerging Memory & Logic Solutions Inc

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