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AD9388ABSTZ-5P Datasheet(PDF) 19 Page - Analog Devices |
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AD9388ABSTZ-5P Datasheet(HTML) 19 Page - Analog Devices |
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19 / 28 page ![]() AD9388A Rev. B | Page 19 of 28 Processor1 Mode/Format Output of Data Port Pins P[19:0] 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CP Mode 17 Video output 30-bit 4:4:4 CHA[9:0] (default data is G[9:0] or Y[9:0]) CHC[9:0] (default data is B[9:0] or Cb[9:0]) CP Mode 18 Video output 30-bit 4:4:4 CHC[9:0] (default data is B[9:0] or Cb[9:0]) CHA[9:0] (default data is G[9:0] or Y[9:0]) CP Mode 19 Video output 30-bit 4:2:2 CHC[9:0] (default data is B[9:0] or Cb[9:0]) CHB[9:0] (default data is R[9:0] or Cr[9:0]) 1 CP processor uses digitizer or HDMI as input. 2 Maximum pixel clock rate of 54 MHz. 3 Maximum pixel clock rate of 170 MHz for the analog digitizer. 4 Maximum pixel clock rate of 165 MHz for HDMI. Table 9. Component Processor Pixel Output Pin Map (P29 to P20) Processor1 Mode/Format Output of Data Port Pins P[29:20] 29 28 27 26 25 24 23 22 21 20 CP Mode 1 Video output 8-bit 4:2:22 – – – – – – – – – – CP Mode 2 Video output 10-bit 4:2:22 – – – – – – – – – – CP Mode 3 Video output 12-bit 4:2:22 – – – – – – YCrCb[1:0] – – CP Mode 4 Video output 12-bit 4:2:2 2 – – – – YCrCb[3:0] – – CP Mode 5 Video output 12-bit 4:2:2 2 – – – – – – – – – – CP Mode 6 Video output 16-bit 4:2:23, 4 – – – – – – – – – – CP Mode 7 Video output 20-bit 4:2:23, 4 – – – – – – – – – – CP Mode 8 Video output 20-bit 4:2:23, 4 Y[1:0] CrCb[1:0] – – – – – – CP Mode 9 Video output 24-bit 4:2:2 3, 4 – – CrCb[1:0] – – Y[1:0] – – CP Mode 10 Video output 24-bit 4:2:23, 4 CrCb[3:0] Y[3:0] – – CP Mode 11 Video output 24-bit 4:2:23, 4 C rCb[11:4] – – CP Mode 12 Video output 24-bit 4:4:43, 4 CHC[7:0] (for example, B[7:0] or Cb[7:0]) – – CP Mode 13 Video output 24-bit 4:4:43, 4 CHB[7:0] (for example, R[7:0] or Cr[7:0]) – – |
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