CybraTech (2000) Ltd.
SOC-3000/i Scale-On-Chip
ASIC
Technical Specification
Revision B
Page i
July, 2002
TABLE OF CONTENTS
LIST OF FIGURES .................................................................................................................................. IV
LIST OF TABLES ......................................................................................................................................V
GENERAL ....................................................................................................................................................1
GENERAL DESCRIPTION ............................................................................................................................2
ADVANTAGES............................................................................................................................................2
SPECIFICATIONS......................................................................................................................................3
ANALOG-TO-DIGITAL CONVERTER (ADC)...............................................................................................3
ADC Converter Main Channel – Wheatstone Bridge (Load Cell)........................................................3
ADC Converter Auxiliary Channel .......................................................................................................3
REFERENCE INPUTS ...................................................................................................................................4
DIGITAL INPUT ..........................................................................................................................................4
DIGITAL OUTPUT.......................................................................................................................................4
FLASH MEMORY........................................................................................................................................4
CPU...........................................................................................................................................................5
FREQUENCY SOURCE INPUT ......................................................................................................................5
POWER SUPPLY AND MONITOR .................................................................................................................5
ENVIRONMENTAL CONDITIONS.................................................................................................................5
ABSOLUTE MAXIMUM RATING* ...............................................................................................................6
OUTLINE DIMENSIONS...............................................................................................................................6
SCALE MAIN BOARD LAYOUT AND ASSEMBLY PROCESS PARAMETERS FOR SOC-3000........................7
PIN CONFIGURATION .............................................................................................................................9
CPU 80C51TBO .........................................................................................................................................21
MEMORY ORGANIZATION .......................................................................................................................22
Flash (Program & Non-Volatile Data) Memory Mapping and Usage ...............................................22
Application Program Start Address ....................................................................................................23
Serial Downloading (In-Circuit Programming)..................................................................................23
Using the Flash for Data Memory ......................................................................................................24
Data Memory Mapping .......................................................................................................................25
Memory Bank Select Register .............................................................................................................25
CPU SFRs and Configuration Registers (CFR)..................................................................................25
INSTRUCTION SET....................................................................................................................................25
RESET ......................................................................................................................................................26
INTERRUPT VECTORS ..............................................................................................................................26
ADC CONTROLLER INTERFACE .......................................................................................................27
CONTROLLER REGISTERS ........................................................................................................................27
Semaphore Register.............................................................................................................................27
Control Register ..................................................................................................................................27
New Zealand ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
