STLS2F02 datasheet(12/49 Pages) STMICROELECTRONICS

12 / 49 page

Interface description

STLS2F02

12/49

2.5

Initialization signals

Table 5 details the initialization signals.

The STLS2F02 processor includes two reset signals:

●

SYSRESETn: This reset signal is the only way to reset whole STLS2F02 processor.

SYSCLK and MEMCLK must provide stable clock when SYSRESETn is valid. The

width of SYSRESETn should be more than one clock period. Internal reset-control

begins to reset the internal logic when the reset signal is invalid. The internal reset is

finished after 64K SYSCLK cycle. The reset exception vector can then be executed.

●

PCI_RESETn: This signal works as an output when the processor works as a system

main bridge. The reset of PCIX devices in the system must be controlled by this signal.

When the processor works as a PCI/PCIX device, the signal works as reset input to the

PCI interface of the processor.

Note:

Resetting the PCI interface when a process is running may cause the processor to stop

working.

PCI_CONFIG defines the working mode of the processor interface. It must be stable during

system reset, so that software can read this value from an internal register after system start

up. The PCI address of the first instruction is 0x1FC0 0000 when system start from PCI is

configured. Otherwise the first instruction is fetched from address 0 of local bus ROM.

Table 5.

Initialization interface signals

Name

Input/output

Description

SYSRESETn

System reset. Low state of the signal must be maintained

more than one SYSCLK period. It can be asynchronous

to SYSCLK

PCI_RESETn

I/O

PCI interface reset

PCI_CONFIG

PCI configuration

undefined

6:5

PCIX BUS speed selection

PCIX BUS mode

Master mode

Start from PCI

External PCI arbitration

16-bit starting ROM

Note:

PCIX BUS mode

PCI 33/66

PCIX 66

PCIX 100

PCIX 133

STLS2F02 Datasheet(PDF) 12 Page - STMicroelectronics

STLS2F02 Datasheet(HTML) 12 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49

Datasheet Download

Link URL