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STLS2F02 Datasheet(PDF) 26 Page - STMicroelectronics

Part # STLS2F02
Description  Loongson 2F high performance 64-bit superscalar MIPS® microprocessor
PDF  49 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STLS2F02 Datasheet(HTML) 26 Page - STMicroelectronics

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DDR2 SDRAM controller interface description
STLS2F02
26/49
CONF_CTL_02[31:0] Offset: 0x20
DDR2 667:0x00000000
NO_CMD_INIT
24:24
0x0
0x0-0x1
Disable DRAM cmds until TDLL has
expired during initialization.
INTRPTWRITENA
16:16
0x0
0x0-0x1
Allow the controller to interrupt a
combined write cmd with auto pre-
charge with another write cmd.
INTRPTREADA
8:8
0x0
0x0-0x1
Allow the controller to interrupt a
combined read with auto pre-charge
cmd with another read cmd.
INTRPTAPBURST
0:0
0x0
0x0-0x1
Allow the controller to interrupt an auto
pre-charge cmd with another cmd.
CONF_CTL_02[63:32]
Offset: 0x20
DDR2 667:0x01000101
PRIORITY_EN
56:56
0x0
0x0-0x1
Enable priority for cmd queue
placement logic.
POWER_DOWN
48:48
0x0
0x0-0x1
Disable clock enable and set DRAMs in
power-down state.
PLACEMENT_EN
40:40
0x0
0x0-0x1
Enable placement logic for cmd queue.
ODT_ADD_TURN_CLK_EN
32:32
0x0
0x0-0x1
Enable extra turn-around clock
between back-to-back reads/writes to
different chip selects.
CONF_CTL_03[31:0]
Offset: 0x30
DDR2 667:0x01000000
RW_SAME_EN
24:24
0x0
0x0-0x1
Enable read/write grouping for cmd
queue placement logic.
REG_DIMM_EN
16:16
0x0
0x0-0x1
Enable registered DIMM operation of
the controller.
REDUC
8:8
0x0
0x0-0x1
Enable the half datapath (32-bit)
feature of the controller.
PWRUP_SREFRESH_EXIT
0:0
0x0
0x0-0x1
Powerup via self-refresh instead of full
memory initialization.
CONF_CTL_03[63:32]
Offset: 0x30
DDR2 667:0x01010000
SWAP_PORT_RW_SAME_EN
56:56
0x0
0x0-0x1
Enable command swapping logic
between commands of the same type
from the same port in execution unit.
SWAP_EN
48:48
0x0
0x0-0x1
Enable command swapping logic in
execution unit.
START
40:40
0x0
0x0-0x1
Initiate cmd processing in the
controller.
SREFRESH
32:32
0x0
0x0-0x1
Place DRAMs in self-refresh mode.
CONF_CTL_04[31:0]
Offset: 0x40
DDR2 667:0x00010101
WRITE_MODEREG
24:24
0x0
0x0-0x1
Write EMRS data to the DRAMs.
WRITE-ONLY
Table 12.
DDR SDRAM configuration parameter register format (continued)
Parameters
Bits
Default
value
Range
Description



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