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S9S08QD2CSC Datasheet(PDF) 86 Page - Freescale Semiconductor, Inc |
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S9S08QD2CSC Datasheet(HTML) 86 Page - Freescale Semiconductor, Inc |
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86 / 202 page  Chapter 7 Central Processor Unit (S08CPUV2) MC9S08QD4 Series MCU Data Sheet, Rev. 3 86 Freescale Semiconductor BRA rel Branch Always (if I = 1) REL 20 rr 3 ppp – – – – – – BRCLR n,opr8a,rel Branch if Bit n in Memory Clear (if (Mn) = 0) DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) 01 03 05 07 09 0B 0D 0F dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 rpppp rpppp rpppp rpppp rpppp rpppp rpppp rpppp – – – – – BRN rel Branch Never (if I = 0) REL 21 rr 3 ppp – – – – – – BRSET n,opr8a,rel Branch if Bit n in Memory Set (if (Mn) = 1) DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) 00 02 04 06 08 0A 0C 0E dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 rpppp rpppp rpppp rpppp rpppp rpppp rpppp rpppp – – – – – BSET n,opr8a Set Bit n in Memory (Mn ← 1) DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) 10 12 14 16 18 1A 1C 1E dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 rfwpp rfwpp rfwpp rfwpp rfwpp rfwpp rfwpp rfwpp – – – – – – BSR rel Branch to Subroutine PC ← (PC) + $0002 push (PCL); SP ← (SP) – $0001 push (PCH); SP ← (SP) – $0001 PC ← (PC) + rel REL AD rr 5 ssppp – – – – – – CBEQ opr8a,rel CBEQA #opr8i,rel CBEQX #opr8i,rel CBEQ oprx8,X+,rel CBEQ ,X+,rel CBEQ oprx8,SP,rel Compare and... Branch if (A) = (M) Branch if (A) = (M) Branch if (X) = (M) Branch if (A) = (M) Branch if (A) = (M) Branch if (A) = (M) DIR IMM IMM IX1+ IX+ SP1 31 41 51 61 71 9E 61 dd rr ii rr ii rr ff rr rr ff rr 5 4 4 5 5 6 rpppp pppp pppp rpppp rfppp prpppp – – – – – – CLC Clear Carry Bit (C ← 0) INH 98 1 p – – – – – 0 CLI Clear Interrupt Mask Bit (I ← 0) INH 9A 1 p – – 0 – – – CLR opr8a CLRA CLRX CLRH CLR oprx8,X CLR ,X CLR oprx8,SP Clear M ← $00 A ← $00 X ← $00 H ← $00 M ← $00 M ← $00 M ← $00 DIR INH INH INH IX1 IX SP1 3F 4F 5F 8C 6F 7F 9E 6F dd ff ff 5 1 1 1 5 4 6 rfwpp p p p rfwpp rfwp prfwpp 0 – – 0 1 – Table 7-2. Instruction Set Summary (Sheet 3 of 9) Source Form Operation Object Code Cyc-by-Cyc Details Affect on CCR VH I N Z C |
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