M38063M9DFP datasheet(39/58 Pages) RENESAS

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Serial I/O1 clock output “H” pulse width

Serial I/O1 clock output “L” pulse width

Serial I/O1 output delay time (Note 1)

Serial I/O1 output valid time (Note 1)

Serial I/O1 clock output rising time

Serial I/O1 clock output falling time

Serial I/O2 clock output “H” pulse width

Serial I/O2 clock output “L” pulse width

Serial I/O2 output delay time

Serial I/O2 output valid time

Serial I/O2 clock output falling time

CMOS output rising time (Note 2)

CMOS output falling time (Note 2)

140

200

Symbol

Parameter

Limits

Min.

Unit

SWITCHING CHARACTERISTICS 1 (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85

°C, unless otherwise noted)

tc(SCLK1)/2–30

–30

tc(SCLK2)/2–160

Typ.

Max.

twH(SCLK1)

twL(SCLK1)

td(SCLK1–TXD)

tv(SCLK1–TXD)

tr(SCLK1)

tf(SCLK1)

twH(SCLK2)

twL(SCLK2)

td(SCLK2–SOUT2)

tv(SCLK2–SOUT2)

tf(SCLK2)

tr(CMOS)

tf(CMOS)

Test conditions

Fig. 32

Fig. 33

Fig. 32

Note1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.

2: Pins XOUT and P70–P77 are excluded.

Serial I/O1 clock output “H” pulse width

Serial I/O1 clock output “L” pulse width

Serial I/O1 output delay time (Note 1)

Serial I/O1 output valid time (Note 1)

Serial I/O1 clock output rising time

Serial I/O1 clock output falling time

Serial I/O2 clock output “H” pulse width

Serial I/O2 clock output “L” pulse width

Serial I/O2 output delay time

Serial I/O2 output valid time

Serial I/O2 clock output falling time

CMOS output rising time (Note 2)

CMOS output falling time (Note 2)

350

400

Symbol

Parameter

Limits

Min.

Unit

SWITCHING CHARACTERISTICS 2 (VCC = 3.0 to 4.0 V, VSS = 0 V, Ta = –20 to 85

°C, unless otherwise noted)

tc(SCLK1)/2–50

–30

tc(SCLK2)/2–240

Typ.

Max.

twH(SCLK1)

twL(SCLK1)

td(SCLK1–TXD)

tv(SCLK1–TXD)

tr(SCLK1)

tf(SCLK1)

twH(SCLK2)

twL(SCLK2)

td(SCLK2–SOUT2)

tv(SCLK2–SOUT2)

tf(SCLK2)

tr(CMOS)

tf(CMOS)

Test conditions

Fig. 32

Fig. 33

Fig. 32

Note1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.

2: Pins XOUT and P70–P77 are excluded.

MITSUBISHI MICROCOMPUTERS

3806 Group

M38063M9DFP Datasheet(PDF) 39 Page - Renesas Technology Corp

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