R8C2K datasheet(293/471 Pages) RENESAS

293 / 471 page

R8C/2K Group, R8C/2L Group

16. Timers

Rev.1.10

Dec 21, 2007

Page 276 of 450

REJ09B0406-0110

Figure 16.116 TRDCR0 Register in Reset Synchronous PWM Mode

Timer RD Control Register 0

(3)

Symbol

Address

After Reset

TRDCR0

0140h

00h

Bit Symbol

Bit Name

Function

NOTES:

3. The TRDCR1 register is not used in reset synchronous PWM mode.

Bits CKEG1 to CKEG0 are enabled w hen bits TCK2 to TCK0 are set to 101b (TRDCLK input) and the STCLK bit in the

TRDFCR register is set to 1 (external clock input enabled).

CKEG1

CCLR0

Set to 001b (TRD0 register cleared at compare

match w ith TRDGRA0 register) in reset

synchronous PWM mode.

TRD0 counter clear select bits

This setting is enabled w hen the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled).

b3 b2

CKEG0

b1 b0

TCK2

001

b7 b6 b5 b4

CCLR2

CCLR1

Count source select bits

b2 b1b0

0 0 0 : f1

0 0 1 : f2

0 1 0 : f4

0 1 1 : f8

1 0 0 : f32

1 0 1 : TRDCLK input(1)

1 1 0 : fOCO40M

1 1 1 : Do not set.

External clock edge select bits(2) b4 b3

0 0 : Count at the rising edge

0 1 : Count at the falling edge

1 0 : Count at both edges

1 1 : Do not set.

TCK1

TCK0

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