R8C2K datasheet(290/471 Pages) RENESAS

290 / 471 page

R8C/2K Group, R8C/2L Group

16. Timers

Rev.1.10

Dec 21, 2007

Page 273 of 450

REJ09B0406-0110

Figure 16.113 Registers TRDSTR and TRDMR in Reset Synchronous PWM Mode

Timer RD Start Register

(1)

Symbol

Address

After Reset

TRDSTR

0137h

11111100b

Bit Symbol

Bit Name

Function

NOTES:

When the CSEL0 bit is set to 1, w rite 0 to the TSTART0 bit.

When the CSEL1 bit is set to 1, w rite 0 to the TSTART1 bit.

When the CSEL0 bit is set to 0 and the compare match signal (TRDIOA0) is generated, this bit is set to 0 (count

stops).

When the CSEL1 bit is set to 0 and the compare match signal (TRDIOA1) is generated, this bit is set to 0 (count

stops).

b3 b2

CSEL1

b1 b0

TSTART0

b7 b6 b5 b4

TSTART1

TRD1 count start flag(5)

0 : Count stops(3)

1 : Count starts

TRD0 count start flag(4)

0 : Count stops(2)

1 : Count starts

TRD0 count operation select bit

0 : Count stops at the compare match w ith

the TRDGRA0 register

1 : Count continues after the compare

match w ith the TRDGRA0 register

CSEL0

—

(b7-b4)

Nothing is assigned. If necessary, set to 0.

When read, the content is 1.

Set the TRDSTR register using the MOV instruction (do not use the bit handling instruction). Refer to 16.4.12.1

TRDSTR Register of Notes on Tim er RD.

TRD1 count operation select bit

0 : Count stops at the compare match w ith

the TRDGRA1 register

1 : Count continues after the compare

match w ith the TRDGRA1 register

—

Timer RD Mode Register

Symbol

Address

After Reset

TRDMR

0138h

00001110b

Bit Symbol

Bit Name

Function

BFC1

BFD1

TRDGRD1 register function select

bit

0 : General register

1 : Buffer register of TRDGRB1 register

TRDGRC0 register function select

bit

0 : General register

1 : Buffer register of TRDGRA0 register

BFC0

TRDGRD0 register function select

bit

0 : General register

1 : Buffer register of TRDGRB0 register

TRDGRC1 register function select

bit

0 : General register

1 : Buffer register of TRDGRA1 register

—

(b3-b1)

—

Timer RD synchronous bit

Set this bit to 0 (registers TRD0 and TRD1

operate independently) in reset synchronous

PWM mode.

Nothing is assigned. If necessary, set to 0.

When read, the content is 1.

b7 b6 b5 b4 b3 b2

BFD0

b1 b0

SYNC

R8C2K Datasheet(PDF) 290 Page - Renesas Technology Corp

R8C2K Datasheet(HTML) 290 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL