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R5F72115D160FPV Datasheet(PDF) 579 Page - Renesas Technology Corp

Part # R5F72115D160FPV
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family
PDF  1228 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R5F72115D160FPV Datasheet(HTML) 579 Page - Renesas Technology Corp

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Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
Rev. 2.00 May. 08, 2008 Page 555 of 1200
REJ09B0344-0200
10.7.8
Contention between Buffer Register Write and TCNT Clear
When the buffer transfer timing is set at the TCNT clear by the buffer transfer mode register
(TBTM), if TCNT clear occurs in the T2 state of a TGR write cycle, the data that is transferred to
TGR by the buffer operation is the data before write.
Figure 10.123 shows the timing in this case.
Address
Write signal
TCNT clear
signal
Buffer transfer
signal
TGR write cycle
T1
T2
Buffer register
address
N
N
M
Buffer register write data
Buffer register
TGR
P
φ
Figure 10.123 Contention between Buffer Register Write and TCNT Clear



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