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R5F72115D160FPV Datasheet(PDF) 580 Page - Renesas Technology Corp |
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R5F72115D160FPV Datasheet(HTML) 580 Page - Renesas Technology Corp |
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580 / 1228 page  Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 2.00 May. 08, 2008 Page 556 of 1200 REJ09B0344-0200 10.7.9 Contention between TGR Read and Input Capture If an input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data in the buffer before input capture transfer for channels 0 to 4, and the data after input capture transfer for channel 5. Figures 10.124 and 125 show the timing in this case. Input capture signal Read signal Address TGR read cycle T1 T2 TGR Internal data bus TGR address P φ N N M Figure 10.124 Contention between TGR Read and Input Capture (Channels 0 to 4) Input capture signal Read signal Address TGR read cycle T1 T2 TGR Internal data bus TGR address P φ M NM Figure 10.125 Contention between TGR Read and Input Capture (Channel 5) |
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