R5F72115D160FPV datasheet(582/1228 Pages) RENESAS

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Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)

Rev. 2.00 May. 08, 2008 Page 558 of 1200

REJ09B0344-0200

10.7.11

Contention between Buffer Register Write and Input Capture

If an input capture signal is generated in the T2 state of a buffer register write cycle, the buffer

operation takes precedence and the write to the buffer register is not performed.

Figure 10.128 shows the timing in this case.

Input capture

signal

Write signal

Address

TCNT

Buffer register write cycle

TGR

Buffer register

address

Figure 10.128 Contention between Buffer Register Write and Input Capture

10.7.12

TCNT2 Write and Overflow/Underflow Contention in Cascade Connection

With timer counters TCNT1 and TCNT2 in a cascade connection, when a contention occurs

during TCNT_1 count (during a TCNT_2 overflow/underflow) in the T

2 state of the TCNT_2

write cycle, the write to TCNT_2 is conducted, and the TCNT_1 count signal is disabled. At this

point, if there is match with TGRA_1 and the TCNT_1 value, a compare signal is issued.

Furthermore, when the TCNT_1 count clock is selected as the input capture source of channel 0,

TGRA_0 to D_0 carry out the input capture operation. In addition, when the compare match/input

capture is selected as the input capture source of TGRB_1, TGRB_1 carries out input capture

operation. The timing is shown in figure 10.129.

For cascade connections, be sure to synchronize settings for channels 1 and 2 when setting TCNT

clearing.

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