R5F72115D160FPV datasheet(641/1228 Pages) RENESAS

641 / 1228 page

Section 12 Port Output Enable 2 (POE2)

Rev. 2.00 May. 08, 2008 Page 617 of 1200

REJ09B0344-0200

12.3.2

Output Level Control/Status Register 1 (OCSR1)

OCSR1 is a 16-bit readable/writable register that controls the enable/disable of both output level

comparison and interrupts, and indicates status.

0000000000000000

R/(W)*1 RRRRR

R/W*2 R/W

RRRRRRRR

Notes:

Only 0 can be written to clear the flag after 1 is read.

Can be modified only once after a power-on reset.

Bit:

Initial value:

R/W:

OSF1

-----

OCE1

OIE1

Bit

Bit Name

Initial

Value

R/W

Description

OSF1

R/(W)*

Output Short Flag 1

Indicates that any one of the three pairs of MTU2 2-

phase outputs to be compared has simultaneously

become an active level.

[Clearing condition]

• By writing 0 to OSF1 after reading OSF1 = 1

[Setting condition]

• When any one of the three pairs of 2-phase outputs

has simultaneously become an active level

14 to 10

⎯

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

OCE1

R/W*

Output Short High-Impedance Enable 1

Specifies whether to place the pins in high-impedance

state when the OSF1 bit in OCSR1 is set to 1.

0: Does not place the pins in high-impedance state

1: Places the pins in high-impedance state

OIE1

R/W

Output Short Interrupt Enable 1

Enables or disables interrupt requests when the OSF1 bit

in OCSR is set to 1.

0: Interrupt requests disabled

1: Interrupt requests enabled

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