R5F72115D160FPV datasheet(642/1228 Pages) RENESAS

642 / 1228 page

Section 12 Port Output Enable 2 (POE2)

Rev. 2.00 May. 08, 2008 Page 618 of 1200

REJ09B0344-0200

Bit

Bit Name

Initial

Value

R/W

Description

7 to 0

⎯

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

Notes: 1. Only 0 can be written to clear the flag after 1 is read.

2. Can be modified only once after a power-on reset.

12.3.3

Input Level Control/Status Register 2 (ICSR2)

ICSR2 is a 16-bit readable/writable register that selects the

POE4 and POE7 pin input modes,

controls the enable/disable of interrupts, and indicates status.

0000000000000000

R/(W)*1

R/W

R/W*2 R/W*2

Notes:

Only 0 can be written to clear the flag after 1 is read.

Can be modified only once after a power-on reset.

Bit:

Initial value:

R/W:

POE7F

POE4F

PIE2

POE7M[1:0]

POE4M[1:0]

Bit

Bit Name

Initial

Value

R/W

Description

POE7F

R/(W)*

POE7 Flag

Indicates that a high impedance request has been input

to the

POE7 pin.

[Clearing conditions]

• By writing 0 to POE7F after reading POE7F = 1

(when the falling edge is selected by bits 7 and 6 in

ICSR2)

• By writing 0 to POE7F after reading POE7F = 1 after

a high level input to

POE7 is sampled at Pφ/8, Pφ/16,

or P

φ/128 clock (when low-level sampling is selected

by bits 7 and 6 in ICSR2)

[Setting condition]

• When the input condition set by bits 7 and 6 in ICSR2

occurs at the

POE7 pin

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