R5F72115D160FPV datasheet(637/1228 Pages) RENESAS

637 / 1228 page

Section 12 Port Output Enable 2 (POE2)

Rev. 2.00 May. 08, 2008 Page 613 of 1200

REJ09B0344-0200

12.3.1

Input Level Control/Status Register 1 (ICSR1)

ICSR1 is a 16-bit readable/writable register that selects the

POE0, POE1, and POE3 pin input

modes, controls the enable/disable of interrupts, and indicates status.

0000000000000000

R/(W)*1

R/(W)*1 R/(W)*1

R/W

R/W*2 R/W*2

R/W*2 R/W*2 R/W*2 R/W*2

Bit:

Initial value:

R/W:

Notes:

Only 0 can be written to clear the flag after 1 is read.

Can be modified only once after a power-on reset.

POE3F

POE1F POE0F

PIE1

POE3M[1:0]

POE1M[1:0]

POE0M[1:0]

Bit

Bit Name

Initial

Value

R/W

Description

POE3F

R/(W)*

POE3 Flag

Indicates that a high impedance request has been input

to the

POE3 pin.

[Clearing conditions]

• By writing 0 to POE3F after reading POE3F = 1

(when the falling edge is selected by bits 7 and 6 in

ICSR1)

• By writing 0 to POE3F after reading POE3F = 1 after

a high level input to

POE3 is sampled at Pφ/8, Pφ/16,

or P

φ/128 clock (when low-level sampling is selected

by bits 7 and 6 in ICSR1)

[Setting condition]

• When the input set by bits 7 and 6 in ICSR1 occurs at

the

POE3 pin

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